VHDL TESTBENCH do zad 18. UCYF 16Z

testbench.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb is
end tb;
architecture arch of tb is

	component kolokwium 
	port (clk,set: in bit; wy: out bit);
	end component;
	
	
	signal set,clk,wy: bit;
	
	begin
	KOL1: kolokwium port map (clk=>clk,set=>set,wy=>wy);
	
	process
		begin 
		clk <= '0';
		wait for 1 ns;
		clk <= '1';
		wait for 1 ns;
	end process;
	
	process
		begin
		set <= '0';
		wait for 5 ns;
		set <= '1';
		wait for 5 ns;
	end process;
	
	
	process
		begin
		wait for 20 ns;
		assert FALSE
		severity FAILURE;
	end process;

end arch;