Wow I was not expecting a Verilog challenge, this language is really fun.
Anyways, this challenge consists of a Verilog file that does a lot of nonsense no one cares to read except for the line assign { y[15], y[7] } = { x[15], x[7] };
, and the output of what this complicated circuit gave when it was fed the flag. The challenge is also lacking an implementation of the logic gates it uses but that is not a problem, we can write it.
As the inputs are wires, the input can take only two values 0 and 1. For once bruteforce seems the only option, and bruteforce seems feasible as there are only $2^{14} = 16384$ different values to test. We will thus write a gates.v
file with the implementation of the basic gates in Verilog and a testbench.v
that will bruteforce this code until finding the correct output. Once we have the correct input we will simply decode it back to ASCII with decode.py
.
To solve the challenge the only thing left is to execute our programs.
We are using Icarus to simulat