Created
April 5, 2018 19:22
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| First chapter | |
| - obstacles/walls of progression | |
| - ILP / POWER / Memory wall | |
| - Multicore | |
| Second chapter: | |
| - Performance | |
| - cpu speed | |
| - clock cycles | |
| - execution time | |
| - metric | |
| - not easy to decide which to choose | |
| - Execution time factors | |
| - utilization | |
| - speedup | |
| - percent speedup | |
| - Benchmarks | |
| - theoretical or practical | |
| Third chapter | |
| - Memory and I/O subsystems | |
| - observations on locality | |
| - organization of memory block in a hierarchy | |
| - The actual hierarchy | |
| - cache memory operation | |
| - Effetive memory access time: formula | |
| - logical/physical/virtual | |
| Fourth Chapter: ILP | |
| - RISC pipelining | |
| - go through terminology | |
| - some formula in slides | |
| - branching | |
| - revised pipeline early branch | |
| - superscalar architecture | |
| - Static vs dynamic scheduling: data dependencies | |
| Fifth: Multicore architecture | |
| - concurrency goal -> increase performance | |
| - hyper threaded processors | |
| - multiprocessors systems: all processors | |
| - design considerations | |
| - scalability of parallel processors | |
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