gistfile1.txt

➜ INTEL_DEBUG=spill_fs,shaders,ann ~/src/sim-drm/build/sim-drm -a ~/src/sim/DG2/AubLoad -p dg2 ~/src/VK-GL-CTS/build/external/vulkancts/modules/vulkan/deqp-vk -n dEQP-VK.api.smoke.triangle
Writing test log into TestResults.qpa
dEQP Core git-a590d9ab4cd2b0c708b6619c744c13311c32cde1 (0xa590d9ab) starting..
  target implementation = 'X11 EGL/GLX'
INFO [GENERAL]  DG2 Fulsim Version 220220-53798-DG2 Feb 20 2022 03:27:00
INFO [GENERAL]  [x64 Build]
INFO [GENERAL]  Fulsim command line: -device dg2.8x4x16.c0 -dumpConfig 
WARNING [DEVICE_MNGR]   Name "Present Render Command Streamer Ids" is not in the m_CommandStreamersConfigurationMap!
WARNING [DEVICE_MNGR]   Name "Present Graphics Security Controller Command Streamer Ids" is not in the m_CommandStreamersConfigurationMap!
Total Runtime: 0.00335515 seconds
        Max VM Usage (VmPeak / PeakPagefileUsage): 105476 KB
        Max VM Residence (VmHWM / PeakWorkingSetSize): 44332 KB
Success
DRM_I915_QUERY: unhandled query id: 65543
MESA: warning: Kernel lacks support for DRM_I915_QUERY_GEOMETRY_SUBSLICES, falling back to broken userspace workaround.
DRM_I915_QUERY: unhandled query id: 65540
DRM_I915_GETPARAM: unhandled param 55
DRM_I915_GETPARAM: unhandled param 56
DRM_I915_QUERY: unhandled query id: 3
DRM_I915_GETPARAM: unhandled param 54
MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0

DRM_I915_QUERY: unhandled query id: 65543
MESA: warning: Kernel lacks support for DRM_I915_QUERY_GEOMETRY_SUBSLICES, falling back to broken userspace workaround.
DRM_I915_QUERY: unhandled query id: 65540
DRM_I915_GETPARAM: unhandled param 55
DRM_I915_GETPARAM: unhandled param 56
DRM_I915_QUERY: unhandled query id: 3
DRM_I915_GETPARAM: unhandled param 54
MESA-INTEL: warning: Performance support disabled, consider sysctl dev.i915.perf_stream_paranoid=0

RCS0: 0x000020ec is a privileged register in a non-privileged batch buffer.
Register write will be Noop-ed!

Test case 'dEQP-VK.api.smoke.triangle'..
NIR (from SPIR-V) for MESA_SHADER_VERTEX shader:
shader: MESA_SHADER_VERTEX
source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
inputs: 0
outputs: 0
uniforms: 0
shared: 0
ray queries: 0
decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 0, 0)
decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = deref_var &@0 (shader_in vec4) 
        vec4 32 ssa_1 = intrinsic load_deref (ssa_0) (access=0)
        vec1 32 ssa_4 = deref_var &@1 (shader_out vec4) 
        intrinsic store_deref (ssa_4, ssa_1) (wrmask=xyzw /*15*/, access=0)
        /* succs: block_1 */
        block block_1:
}

NIR (from SPIR-V) for MESA_SHADER_FRAGMENT shader:
shader: MESA_SHADER_FRAGMENT
source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
inputs: 0
outputs: 0
uniforms: 0
shared: 0
ray queries: 0
decl_var shader_out INTERP_MODE_NONE mediump vec4 @0 (FRAG_RESULT_DATA0.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec4 32 ssa_0 = load_const (0x3f800000, 0x00000000, 0x3f800000, 0x3f800000) = (1.000000, 0.000000, 1.000000, 1.000000)
        vec1 32 ssa_1 = deref_var &@0 (shader_out vec4) 
        intrinsic store_deref (ssa_1, ssa_0) (wrmask=xyzw /*15*/, access=0)
        /* succs: block_1 */
        block block_1:
}

NIR (SSA form) for vertex shader:
shader: MESA_SHADER_VERTEX
source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
inputs: 0
outputs: 0
uniforms: 0
shared: 0
ray queries: 0
decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/)
        /* succs: block_1 */
        block block_1:
}

NIR (final form) for vertex shader:
shader: MESA_SHADER_VERTEX
source_sha1: {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}
inputs: 0
outputs: 0
uniforms: 0
shared: 0
ray queries: 0
decl_var shader_in INTERP_MODE_NONE vec4 @0 (VERT_ATTRIB_GENERIC0.xyzw, 15, 0)
decl_var shader_out INTERP_MODE_NONE vec4 @1 (VARYING_SLOT_POS.xyzw, 0, 0)
decl_function main (0 params)

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32 /*160*/, io location=15 slots=1 /*143*/)
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw /*15*/, component=0, src_type=float32 /*160*/, io location=0 slots=1 /*128*/, xfb() /*0*/, xfb2() /*0*/)
        /* succs: block_1 */
        block block_1:
}

VS Output VUE map (4 slots, SSO)
  [0] VARYING_SLOT_PSIZ
  [1] VARYING_SLOT_POS
  [2] VARYING_SLOT_CLIP_DIST0
  [3] VARYING_SLOT_CLIP_DIST1

Native code for unnamed vertex shader (null) (sha1 7429d1686d91fe2c7424ec988f4f41c073159648)
SIMD8 shader: 57 instructions. 0 loops. 348 cycles. 0:0 spills:fills, 11 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 912 to 912 bytes (0%)
   START B0 (348 cycles)
and(8)          g6<1>UD         g0.5<0,1,0>UD   0xfffffc00UD    { align1 WE_all 1Q };
   URB write
mov(8)          g8<1>UD         g1<8,8,1>UD                     { align1 WE_all 1Q };
mov(1)          g7<1>UD         0x00000000UD                    { align1 WE_all 1N };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000010fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         nullUD          g7UD            g8UD            0x22003504                a0.1<0>UD
                            ugm MsgDesc: ( store, a32, d32, V4, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $0 };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $0.src };
mov(8)          g9<1>F          g2<8,8,1>F                      { align1 1Q };
mov(1)          g7<1>UD         0x00000800UD                    { align1 WE_all 1N $0.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $0.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N A@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000010fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         nullUD          g7UD            g9UD            0x22003504                a0.1<0>UD
                            ugm MsgDesc: ( store, a32, d32, V4, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 1Q @1 $1 };
mov(8)          g10<1>F         g3<8,8,1>F                      { align1 1Q $1.src };
mov(1)          g7<1>UD         0x00001000UD                    { align1 WE_all 1N $1.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $1.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N A@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000010fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         nullUD          g7UD            g10UD           0x22003504                a0.1<0>UD
                            ugm MsgDesc: ( store, a32, d32, V4, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 1Q @1 $2 };
mov(8)          g11<1>F         g4<8,8,1>F                      { align1 1Q $2.src };
mov(1)          g7<1>UD         0x00001800UD                    { align1 WE_all 1N $2.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $2.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N A@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000010fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         nullUD          g7UD            g11UD           0x22003504                a0.1<0>UD
                            ugm MsgDesc: ( store, a32, d32, V4, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 1Q @1 $3 };
mov(8)          g12<1>F         g5<8,8,1>F                      { align1 1Q $3.src };
mov(1)          g7<1>UD         0x00002000UD                    { align1 WE_all 1N $3.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $3.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N A@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000010fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         nullUD          g7UD            g12UD           0x22003504                a0.1<0>UD
                            ugm MsgDesc: ( store, a32, d32, V4, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 1Q @1 $4 };
mov(1)          g7<1>UD         0x00000000UD                    { align1 WE_all 1N $4.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000000fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         g122UD          g7UD            nullUD          0x22503500                a0.1<0>UD
                            ugm MsgDesc: ( load, a32, d32, V4, L1STATE_L3MOCS dst_len = 5, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $5 };
mov(1)          g7<1>UD         0x00000800UD                    { align1 WE_all 1N $5.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000000fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         g123UD          g7UD            nullUD          0x22503500                a0.1<0>UD
                            ugm MsgDesc: ( load, a32, d32, V4, L1STATE_L3MOCS dst_len = 5, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $6 };
mov(1)          g7<1>UD         0x00001000UD                    { align1 WE_all 1N $6.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000000fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         g124UD          g7UD            nullUD          0x22503500                a0.1<0>UD
                            ugm MsgDesc: ( load, a32, d32, V4, L1STATE_L3MOCS dst_len = 5, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $7 };
mov(1)          g7<1>UD         0x00001800UD                    { align1 WE_all 1N $7.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000000fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         g125UD          g7UD            nullUD          0x22503500                a0.1<0>UD
                            ugm MsgDesc: ( load, a32, d32, V4, L1STATE_L3MOCS dst_len = 5, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $8 };
mov(1)          g7<1>UD         0x00002000UD                    { align1 WE_all 1N $8.src };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N I@1 };
or(1)           a0.1<1>UD       g6<8,8,1>UD     0x0000000fUD    { align1 WE_all 1N };
        ERROR: ExecSize must be greater than or equal to Width
        ERROR: A source cannot span more than 2 adjacent GRF registers
send(8)         g126UD          g7UD            nullUD          0x22503500                a0.1<0>UD
                            ugm MsgDesc: ( load, a32, d32, V4, L1STATE_L3MOCS dst_len = 5, src0_len = 1, src1_len = 0 bss ) surface_state_index 0  { align1 WE_all 1Q @1 $9 };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $5.dst };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $6.dst };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $7.dst };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $8.dst };
sync nop(1)                     null<0,1,0>UB                   { align1 WE_all 1N $9.dst };
send(8)         nullUD          g122UD          nullUD          0x0a080017                0x00000000
                            urb MsgDesc: offset 1 SIMD8 write mlen 5 ex_mlen 0 rlen 0 { align1 1Q @1 $10 EOT };
   END B0

deqp-vk: ../src/intel/compiler/brw_fs_generator.cpp:2698: int fs_generator::generate_code(const cfg_t*, int, shader_stats, const brw::performance&, brw_compile_stats*): Assertion `validated' failed.