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NAME LAB3A | |
;***************************************************************************** | |
; B E G I N N I N G O F P R O G R A M | |
;***************************************************************************** | |
;----------------------------------------------------------------------------- | |
; E Q U A T E S | |
;----------------------------------------------------------------------------- | |
; 8255 Setup | |
CNTR_8255 EQU 0FFFEH ;Port control address | |
OUTPUT_MODE EQU 0B5H ;Set up mode for port B output | |
; 8253 Setup | |
COUNT_CNTR EQU 000EH ;counter control register address | |
MODE2 EQU 74H ;_____Control Word to Set Counter 0 to Rate Generator Mode | |
MODE3 EQU 36H ;_____Control Word to set Counter 1 to Square Wave Generator Mode | |
COUNT0 EQU 0008H ;counter0 address | |
COUNT1 EQU 000AH ;counter1 address | |
LOPT100uSEC EQU 0F5H ;____Low Point for 100 uSec interval | |
HIPT100uSEC EQU 00H ;____High Point for 100 uSec interval (counter decrements) | |
LOPT200uSEC EQU 02H ;____Low Point for 200 uSec interval | |
HIPT200uSEC EQU 00H ;____High Point for 200 uSec interval (counter decrements) | |
; 8259A Setup | |
CLR_A0 EQU 0000H ;Which CW's written here? ____Control register address where A0=0 | |
SET_A0 EQU 0002H ;Which CW's written here? ____Control register address where A0=1 | |
ICW1 EQU 17H ;____Edge Triggered, call interval of 4, single mode, ICW4 needed | |
ICW2 EQU 20H ;____Set Vector Address for IR0 to T5=1 | |
ICW4 EQU 03H ;____Not special mode, Non-Buffered Mode, Auto EOI, 8086/8 Mode | |
OCW1 EQU 0FCH ;____Enable interrupts 0 and 1, mask rest | |
;----------------------------------------------------------------------------- | |
; S T A R T O F V E C T O R S E G M E N T | |
;----------------------------------------------------------------------------- | |
VECTOR_SEG SEGMENT | |
ORG 00080H ;Interrupt vector: type 32 dec. | |
IR0_IP_VECT DW ? ;Low contains IP of ISR0 | |
IR0_CS_VECT DW ? ;High contains CS of ISR0 | |
IR1_IP_VECT DW ? ;Low contains IP of ISR1 | |
IR1_CS_VECT DW ? ;High contains CS of ISR1 | |
VECTOR_SEG ENDS | |
;----------------------------------------------------------------------------- | |
; S T A R T O F C O D E S E G M E N T | |
;----------------------------------------------------------------------------- | |
CODE_SEG SEGMENT | |
ASSUME CS:CODE_SEG, DS:DATA_SEG | |
ORG 00100H | |
;.............................................................................. | |
; PROCEDURE : INIT | |
; | |
; - This procedure is called from the main program to initialize the | |
; 8253, the 8259A and the 8255. | |
;.............................................................................. | |
INIT PROC NEAR | |
ASSUME DS:DATA_SEG ;offset relative to data_seg | |
;Initialize the 8255 to set port B as output to DAC. | |
MOV DX,CNTR_8255 ; Port control address | |
MOV AL,OUTPUT_MODE ; Set up mode for port B output | |
OUT DX,AL | |
;Initialize 8253 counter0 and counter1 - counter2 is not used. | |
;Clock is the peripheral clock with frequency assumed to be 2.45MHz | |
;___Counter 0 to generate square waves with a period of 100 uSec | |
;___Counter 1 to generate pulses with period of 200 uSec | |
MOV DX,COUNT_CNTR ;_____Set Counter 0 to mode 3: Square Wave Generator | |
MOV AL,MODE3 | |
OUT DX,AL | |
MOV DX,COUNT0 | |
MOV AL,LOPT100uSEC ;_____Set counter 0 interval to 100 uSec | |
OUT DX,AL | |
MOV AL,HIPT100uSEC | |
OUT DX,AL | |
MOV DX,COUNT_CNTR ;_____Set Counter 1 to mode 2: Rate Generator | |
MOV AL,MODE2 | |
OUT DX,AL | |
MOV DX,COUNT1 | |
MOV AL,LOPT200uSEC ;_____Set counter 1 interval to 200 uSec | |
OUT DX,AL | |
MOV AL,HIPT200uSEC | |
OUT DX,AL | |
; Initialize 8259A to : _____First ICW1 is used to set Edge Triggered mode, | |
; call interval of 4 and set to single mode, ICW4 needed. A0 = 0 at this | |
; point because we are doing ICW1. Then ICW2 is set (A0 = 1). ICW2 Sets the | |
; Vector Address for IR0 to T5=1 so we are using IR0 for interrupts. | |
; No ICW3 is used. ICW4 is used where its not special fully nested mode, | |
; Non-Buffered Mode, Auto EOI (End of interrupt) and obviously 8086/8 Mode. | |
MOV DX,CLR_A0 ;_____Write ICW1 to the control register with A0=0 | |
MOV AL,ICW1 | |
OUT DX,AL | |
MOV DX,SET_A0 ;_____Write ICW2 to the control register with A0=1 | |
MOV AL,ICW2 | |
OUT DX,AL | |
MOV AL,ICW4 ;_____Write ICW4 to the control register with A0=1 | |
OUT DX,AL | |
MOV AL,OCW1 ;_____Write OCW1 to the control register with A0=1 | |
OUT DX,AL | |
;Initialization complete, interrupts still disabled. | |
RET | |
INIT ENDP | |
;.............................................................................. | |
; INTERRUPT SERVICE ROUTINE : ISR0 | |
;.............................................................................. | |
ISR0 PROC NEAR | |
IRET | |
ISR0 ENDP | |
;.............................................................................. | |
; INTERRUPT SERVICE ROUTINE : ISR1 | |
;.............................................................................. | |
ISR1 PROC NEAR | |
IRET | |
ISR1 ENDP | |
;.............................................................................. | |
; S T A R T O F M A I N P R O G R A M | |
;.............................................................................. | |
ASSUME DS:VECTOR_SEG ;offset relative to vector_seg | |
;Set up the interrupt vectors. | |
BEG: CLI ;Ensure no interrupt occurs. | |
MOV AX,VECTOR_SEG ;DS = vector_seg | |
MOV DS,AX | |
MOV IR0_IP_VECT,OFFSET ISR0 ;load all ISR's IP and CS | |
MOV IR1_IP_VECT,OFFSET ISR1 | |
MOV AX,CS | |
MOV IR0_CS_VECT,AX | |
MOV IR1_CS_VECT,AX | |
ASSUME DS:DATA_SEG ;offset relative to data_seg | |
MOV AX,DATA_SEG ;Define data segment | |
MOV DS,AX | |
CALL INIT ;Initialization | |
STI ;Enable the interrupt now. | |
LOOP1: | |
JMP LOOP1 | |
CODE_SEG ENDS | |
;---------------------------------------------------------------------------- | |
; S T A R T O F D A T A S E G M E N T | |
;---------------------------------------------------------------------------- | |
DATA_SEG SEGMENT | |
DAC_MEMORY DB 0 ;Store the current DAC value | |
GARBAGE DB 0 ;Store the garbage character. | |
DATA_SEG ENDS | |
END BEG | |
;****************************************************************************** | |
; E N D O F P R O G R A M | |
;****************************************************************************** |
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