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Introduction RISCV-ISAC: RISC-V ISAC is an ISA coverage extraction tool. Given a set of coverpoints and an execution trace of a test/application run on a model, ISAC can provide a report indicating in detail which of those coverpoints were covered by the test/application. ISAC also holds the capability to provide a detailed quality analysis on data propagation occurring within the test/application.

Feature additions on ISAC:

• Instruction object improvement (link)
• Improve data propagation reports to capture multiple signatures per coverpoint (link)
• Explicitly specify redundant coverpoints in the terminal messages ((link)

Introduction RISCV-CTG: RISCV-CTG is the RISC-V based Compatibility Test Generator. This tool is used to generate tests used in the official RISC-V Architectural Test Suite and the RISC-V

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Questions

The first task is mandatory and selection will be based on the performance in the task. The second task is optional and a nice to have.

1. Write a python program which takes a valid RISC-V ISA string(described in Chapter 27 of the RISC-V specification(unpriv)) and generates coverpoints for each of the relevant bits in the extension field of misa register described in section 3.1.1 of the RISC-V privileged ISA. Briefly describe the events (i.e list out the possible exceptions and why) in the test which will occur while testing one such coverpoint. Refer to the csr_comb node described here to understand the format for the coverpoints. Example: for RV32IM, two relevant coverpoints are to check whether the bit at ind