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Pynq build for Pynq-Z1
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| Compiled with: | |
| $ make BOARDS=Pynq-Z1 PREBUILT=/home/<user>/Downloads/bionic.arm.2.5.img |& tee pynq-z1.log | |
| ------------------------------------------------------------------------------------------- | |
| /opt/qemu/bin/qemu-arm-static -version | fgrep 4.0.0 | |
| qemu-arm version 4.0.0 | |
| vivado -version | fgrep 2019.1 | |
| Vivado v2019.1 (64-bit) | |
| xsdk -version | fgrep 2019.1 | |
| ****** SDK v2019.1 (64-bit) | |
| which petalinux-config | fgrep 2019.1 | |
| /opt/pkg/petalinux/2019.1/tools/common/petalinux/bin/petalinux-config | |
| which arm-linux-gnueabihf-gcc | |
| /opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc | |
| which microblaze-xilinx-elf-gcc | |
| /opt/pkg/petalinux/2019.1/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc | |
| which ct-ng | |
| /opt/crosstool-ng/bin/ct-ng | |
| which python | fgrep /usr/bin/python | |
| /usr/bin/python | |
| sudo -n mount > /dev/null | |
| bash /home/pcarr/PYNQ/sdbuild/scripts/check_env.sh | |
| bash /home/pcarr/PYNQ/sdbuild/scripts/check_mounts.sh | |
| mkdir -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1 | |
| cp /home/pcarr/PYNQ/sdbuild/boot/image_arm.its /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/image.its | |
| rm -rf /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp | |
| mkdir -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp | |
| BSP= BSP_BUILD=/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz1-2019.1 /home/pcarr/PYNQ/sdbuild/scripts/create_bsp.sh /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1 zynq | |
| + set -e | |
| + board=/home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1 | |
| + template=zynq | |
| + '[' '!' -z '' ']' | |
| + cp -rf /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/hardware_project /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/meta-user /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp | |
| + cd /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project | |
| + '[' -e makefile ']' | |
| + make | |
| make[1]: Entering directory '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project' | |
| vivado -mode batch -source \ | |
| pynqz1.tcl build_bitstream.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source pynqz1.tcl -notrace | |
| INFO: [BD_TCL-3] Currently there is no design <pynqz1> in project, so creating one... | |
| Wrote : </home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> | |
| INFO: [BD_TCL-4] Making design <pynqz1> as current_bd_design. | |
| INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "pynqz1". | |
| CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. | |
| CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. | |
| CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. | |
| CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. | |
| Wrote : </home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> | |
| source build_bitstream.tcl -notrace | |
| Wrote : </home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/pynqz1.bd> | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v | |
| INFO: [BD 41-1662] The design 'pynqz1.bd' is already validated. Therefore parameter propagation will not be re-run. | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/sim/pynqz1.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hdl/pynqz1_wrapper.v | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 . | |
| Exporting to file /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1.hwh | |
| Generated Block Design Tcl file /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/hw_handoff/pynqz1_bd.tcl | |
| Generated Hardware Definition File /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/synth/pynqz1.hwdef | |
| [Fri Nov 1 16:25:02 2019] Launched pynqz1_ps7_0_synth_1, synth_1... | |
| Run output will be captured here: | |
| pynqz1_ps7_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/pynqz1_ps7_0_synth_1/runme.log | |
| synth_1: /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/synth_1/runme.log | |
| [Fri Nov 1 16:25:02 2019] Launched impl_1... | |
| Run output will be captured here: /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/runme.log | |
| launch_runs: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1696.477 ; gain = 100.238 ; free physical = 12839 ; free virtual = 15263 | |
| [Fri Nov 1 16:25:02 2019] Waiting for impl_1 to finish... | |
| *** Running vivado | |
| with args -log pynqz1_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pynqz1_wrapper.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source pynqz1_wrapper.tcl -notrace | |
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.1/data/ip'. | |
| Command: link_design -top pynqz1_wrapper -part xc7z020clg400-1 | |
| Design is defaulting to srcset: sources_1 | |
| Design is defaulting to constrset: constrs_1 | |
| INFO: [Device 21-403] Loading part xc7z020clg400-1 | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.dcp' for cell 'pynqz1_i/ps7' | |
| INFO: [Project 1-479] Netlist was created with Vivado 2019.1 | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.srcs/sources_1/bd/pynqz1/ip/pynqz1_ps7_0/pynqz1_ps7_0.xdc] for cell 'pynqz1_i/ps7/inst' | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1735.984 ; gain = 0.000 ; free physical = 12229 ; free virtual = 14717 | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| No Unisim elements were transformed. | |
| 9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| link_design completed successfully | |
| link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1735.984 ; gain = 292.672 ; free physical = 12229 ; free virtual = 14717 | |
| Command: opt_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command opt_design | |
| Starting DRC Task | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Project 1-461] DRC finished with 0 Errors | |
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |
| Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.95 . Memory (MB): peak = 1790.645 ; gain = 54.660 ; free physical = 12225 ; free virtual = 14714 | |
| Starting Cache Timing Information Task | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Ending Cache Timing Information Task | Checksum: cd682186 | |
| Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2143.621 ; gain = 352.977 ; free physical = 11835 ; free virtual = 14338 | |
| Starting Logic Optimization Task | |
| Phase 1 Retarget | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |
| Phase 1 Retarget | Checksum: 17442f696 | |
| Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14220 | |
| INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells | |
| Phase 2 Constant propagation | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| Phase 2 Constant propagation | Checksum: 17442f696 | |
| Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14220 | |
| INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells | |
| Phase 3 Sweep | |
| Phase 3 Sweep | Checksum: 13f911416 | |
| Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14220 | |
| INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 89 cells | |
| Phase 4 BUFG optimization | |
| Phase 4 BUFG optimization | Checksum: 13f911416 | |
| Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14220 | |
| INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. | |
| Phase 5 Shift Register Optimization | |
| INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |
| Phase 5 Shift Register Optimization | Checksum: 13f911416 | |
| Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14219 | |
| INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |
| Phase 6 Post Processing Netlist | |
| Phase 6 Post Processing Netlist | Checksum: 13f911416 | |
| Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14219 | |
| INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |
| Opt_design Change Summary | |
| ========================= | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| | Retarget | 0 | 24 | 0 | | |
| | Constant propagation | 0 | 0 | 0 | | |
| | Sweep | 0 | 89 | 0 | | |
| | BUFG optimization | 0 | 0 | 0 | | |
| | Shift Register Optimization | 0 | 0 | 0 | | |
| | Post Processing Netlist | 0 | 0 | 0 | | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| Starting Connectivity Check Task | |
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11717 ; free virtual = 14219 | |
| Ending Logic Optimization Task | Checksum: 149ea6fbb | |
| Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2259.559 ; gain = 0.000 ; free physical = 11716 ; free virtual = 14219 | |
| Starting Power Optimization Task | |
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |
| Ending Power Optimization Task | Checksum: 149ea6fbb | |
| Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2269.465 ; gain = 9.906 ; free physical = 11716 ; free virtual = 14219 | |
| Starting Final Cleanup Task | |
| Ending Final Cleanup Task | Checksum: 149ea6fbb | |
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.465 ; gain = 0.000 ; free physical = 11716 ; free virtual = 14219 | |
| Starting Netlist Obfuscation Task | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.465 ; gain = 0.000 ; free physical = 11716 ; free virtual = 14219 | |
| Ending Netlist Obfuscation Task | Checksum: 149ea6fbb | |
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.465 ; gain = 0.000 ; free physical = 11716 ; free virtual = 14219 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 26 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| opt_design completed successfully | |
| opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2269.465 ; gain = 533.480 ; free physical = 11716 ; free virtual = 14219 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.465 ; gain = 0.000 ; free physical = 11716 ; free virtual = 14219 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2307.418 ; gain = 5.938 ; free physical = 11706 ; free virtual = 14212 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_opt.dcp' has been generated. | |
| INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx | |
| Command: report_drc -file pynqz1_wrapper_drc_opted.rpt -pb pynqz1_wrapper_drc_opted.pb -rpx pynqz1_wrapper_drc_opted.rpx | |
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_opted.rpt. | |
| report_drc completed successfully | |
| Command: place_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Running DRC as a precondition to command place_design | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Placer Task | |
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs | |
| Phase 1 Placer Initialization | |
| Phase 1.1 Placer Initialization Netlist Sorting | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11705 ; free virtual = 14210 | |
| Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ecb84c30 | |
| Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11705 ; free virtual = 14210 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11705 ; free virtual = 14210 | |
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ecb84c30 | |
| Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14205 | |
| Phase 1.3 Build Placer Netlist Model | |
| Phase 1.3 Build Placer Netlist Model | Checksum: 13afeb562 | |
| Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14206 | |
| Phase 1.4 Constrain Clocks/Macros | |
| Phase 1.4 Constrain Clocks/Macros | Checksum: 13afeb562 | |
| Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14207 | |
| Phase 1 Placer Initialization | Checksum: 13afeb562 | |
| Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14207 | |
| Phase 2 Final Placement Cleanup | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14207 | |
| Phase 2 Final Placement Cleanup | Checksum: 13afeb562 | |
| Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14207 | |
| INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed | |
| Ending Placer Task | Checksum: ecb84c30 | |
| Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11699 ; free virtual = 14207 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 43 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| place_design completed successfully | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11701 ; free virtual = 14209 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11694 ; free virtual = 14204 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_placed.dcp' has been generated. | |
| INFO: [runtcl-4] Executing : report_io -file pynqz1_wrapper_io_placed.rpt | |
| report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11688 ; free virtual = 14196 | |
| INFO: [runtcl-4] Executing : report_utilization -file pynqz1_wrapper_utilization_placed.rpt -pb pynqz1_wrapper_utilization_placed.pb | |
| INFO: [runtcl-4] Executing : report_control_sets -verbose -file pynqz1_wrapper_control_sets_placed.rpt | |
| report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2385.258 ; gain = 0.000 ; free physical = 11696 ; free virtual = 14205 | |
| Command: route_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command route_design | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Routing Task | |
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs | |
| Checksum: PlaceDB: 98566580 ConstDB: 0 ShapeSum: 5461e6b0 RouteDB: 0 | |
| Phase 1 Build RT Design | |
| Phase 1 Build RT Design | Checksum: 11a0bcd3c | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2422.754 ; gain = 37.496 ; free physical = 11562 ; free virtual = 14072 | |
| Post Restoration Checksum: NetGraph: af787cf2 NumContArr: 6a93504a Constraints: 0 Timing: 0 | |
| Phase 2 Router Initialization | |
| Phase 2.1 Create Timer | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Phase 2.1 Create Timer | Checksum: 11a0bcd3c | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2448.562 ; gain = 63.305 ; free physical = 11559 ; free virtual = 14068 | |
| Phase 2.2 Fix Topology Constraints | |
| Phase 2.2 Fix Topology Constraints | Checksum: 11a0bcd3c | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2448.562 ; gain = 63.305 ; free physical = 11541 ; free virtual = 14051 | |
| Phase 2.3 Pre Route Cleanup | |
| Phase 2.3 Pre Route Cleanup | Checksum: 11a0bcd3c | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2448.562 ; gain = 63.305 ; free physical = 11541 ; free virtual = 14051 | |
| Number of Nodes with overlaps = 0 | |
| Phase 2.4 Update Timing | |
| Phase 2.4 Update Timing | Checksum: cbf8d822 | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2455.277 ; gain = 70.020 ; free physical = 11538 ; free virtual = 14048 | |
| Phase 2 Router Initialization | Checksum: cbf8d822 | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:13 . Memory (MB): peak = 2455.277 ; gain = 70.020 ; free physical = 11538 ; free virtual = 14048 | |
| Router Utilization Summary | |
| Global Vertical Routing Utilization = 0 % | |
| Global Horizontal Routing Utilization = 0 % | |
| Routable Net Status* | |
| *Does not include unroutable nets such as driverless and loadless. | |
| Run report_route_status for detailed report. | |
| Number of Failed Nets = 130 | |
| (Failed Nets is the sum of unrouted and partially routed nets) | |
| Number of Unrouted Nets = 130 | |
| Number of Partially Routed Nets = 0 | |
| Number of Node Overlaps = 0 | |
| Phase 3 Initial Routing | |
| Number of Nodes with overlaps = 0 | |
| Phase 3 Initial Routing | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 4 Rip-up And Reroute | |
| Phase 4.1 Global Iteration 0 | |
| Phase 4.1 Global Iteration 0 | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 4 Rip-up And Reroute | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 5 Delay and Skew Optimization | |
| Phase 5.1 Delay CleanUp | |
| Phase 5.1 Delay CleanUp | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 5.2 Clock Skew Optimization | |
| Phase 5.2 Clock Skew Optimization | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 5 Delay and Skew Optimization | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 6 Post Hold Fix | |
| Phase 6.1 Hold Fix Iter | |
| Phase 6.1.1 Update Timing | |
| Phase 6.1.1 Update Timing | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 6.1 Hold Fix Iter | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 6 Post Hold Fix | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11535 ; free virtual = 14045 | |
| Phase 7 Route finalize | |
| Router Utilization Summary | |
| Global Vertical Routing Utilization = 0 % | |
| Global Horizontal Routing Utilization = 0 % | |
| Routable Net Status* | |
| *Does not include unroutable nets such as driverless and loadless. | |
| Run report_route_status for detailed report. | |
| Number of Failed Nets = 0 | |
| (Failed Nets is the sum of unrouted and partially routed nets) | |
| Number of Unrouted Nets = 0 | |
| Number of Partially Routed Nets = 0 | |
| Number of Node Overlaps = 0 | |
| Phase 7 Route finalize | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2458.984 ; gain = 73.727 ; free physical = 11534 ; free virtual = 14045 | |
| Phase 8 Verifying routed nets | |
| Verification completed successfully | |
| Phase 8 Verifying routed nets | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2459.984 ; gain = 74.727 ; free physical = 11534 ; free virtual = 14044 | |
| Phase 9 Depositing Routes | |
| Phase 9 Depositing Routes | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2459.984 ; gain = 74.727 ; free physical = 11534 ; free virtual = 14044 | |
| Phase 10 Post Router Timing | |
| Phase 10 Post Router Timing | Checksum: 3de5fc8d | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2459.984 ; gain = 74.727 ; free physical = 11534 ; free virtual = 14044 | |
| INFO: [Route 35-16] Router Completed Successfully | |
| Time (s): cpu = 00:00:17 ; elapsed = 00:00:14 . Memory (MB): peak = 2459.984 ; gain = 74.727 ; free physical = 11551 ; free virtual = 14062 | |
| Routing Is Done. | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 56 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| route_design completed successfully | |
| route_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:15 . Memory (MB): peak = 2459.984 ; gain = 74.727 ; free physical = 11553 ; free virtual = 14063 | |
| INFO: [Common 17-600] The following parameters have non-default value. | |
| general.maxThreads | |
| Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2459.984 ; gain = 0.000 ; free physical = 11553 ; free virtual = 14063 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2471.859 ; gain = 11.875 ; free physical = 11541 ; free virtual = 14053 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_routed.dcp' has been generated. | |
| INFO: [runtcl-4] Executing : report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx | |
| Command: report_drc -file pynqz1_wrapper_drc_routed.rpt -pb pynqz1_wrapper_drc_routed.pb -rpx pynqz1_wrapper_drc_routed.rpx | |
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_drc_routed.rpt. | |
| report_drc completed successfully | |
| INFO: [runtcl-4] Executing : report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx | |
| Command: report_methodology -file pynqz1_wrapper_methodology_drc_routed.rpt -pb pynqz1_wrapper_methodology_drc_routed.pb -rpx pynqz1_wrapper_methodology_drc_routed.rpx | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| INFO: [DRC 23-133] Running Methodology with 4 threads | |
| INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project/pynqz1/pynqz1.runs/impl_1/pynqz1_wrapper_methodology_drc_routed.rpt. | |
| report_methodology completed successfully | |
| INFO: [runtcl-4] Executing : report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx | |
| Command: report_power -file pynqz1_wrapper_power_routed.rpt -pb pynqz1_wrapper_power_summary_routed.pb -rpx pynqz1_wrapper_power_routed.rpx | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Running Vector-less Activity Propagation... | |
| Finished Running Vector-less Activity Propagation | |
| 69 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| report_power completed successfully | |
| INFO: [runtcl-4] Executing : report_route_status -file pynqz1_wrapper_route_status.rpt -pb pynqz1_wrapper_route_status.pb | |
| INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file pynqz1_wrapper_timing_summary_routed.rpt -pb pynqz1_wrapper_timing_summary_routed.pb -rpx pynqz1_wrapper_timing_summary_routed.rpx -warn_on_violation | |
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs | |
| INFO: [runtcl-4] Executing : report_incremental_reuse -file pynqz1_wrapper_incremental_reuse_routed.rpt | |
| INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. | |
| INFO: [runtcl-4] Executing : report_clock_utilization -file pynqz1_wrapper_clock_utilization_routed.rpt | |
| INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file pynqz1_wrapper_bus_skew_routed.rpt -pb pynqz1_wrapper_bus_skew_routed.pb -rpx pynqz1_wrapper_bus_skew_routed.rpx | |
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. | |
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs | |
| Command: write_bitstream -force pynqz1_wrapper.bit | |
| Attempting to get a license for feature 'Implementation' and/or device 'xc7z020' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020' | |
| Running DRC as a precondition to command write_bitstream | |
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado 12-3199] DRC finished with 0 Errors | |
| INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. | |
| INFO: [Designutils 20-2272] Running write_bitstream with 4 threads. | |
| Loading data files... | |
| Loading site data... | |
| Loading route data... | |
| Processing options... | |
| Creating bitmap... | |
| Creating bitstream... | |
| Writing bitstream ./pynqz1_wrapper.bit... | |
| INFO: [Vivado 12-1842] Bitgen Completed Successfully. | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 87 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
| write_bitstream completed successfully | |
| write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 2828.164 ; gain = 292.668 ; free physical = 11515 ; free virtual = 14036 | |
| INFO: [Common 17-206] Exiting Vivado at Fri Nov 1 16:26:56 2019... | |
| [Fri Nov 1 16:26:56 2019] impl_1 finished | |
| wait_on_run: Time (s): cpu = 00:01:52 ; elapsed = 00:01:54 . Memory (MB): peak = 1696.477 ; gain = 0.000 ; free physical = 12741 ; free virtual = 15263 | |
| INFO: [Common 17-206] Exiting Vivado at Fri Nov 1 16:26:56 2019... | |
| [32mBuilt pynqz1 successfully! | |
| (B[m | |
| make[1]: Leaving directory '/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project' | |
| + cd /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp | |
| + petalinux-create --type project --template zynq --name xilinx-pynqz1-2019.1 | |
| INFO: Create project: xilinx-pynqz1-2019.1 | |
| INFO: New project successfully created in /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1 | |
| + cd xilinx-pynqz1-2019.1 | |
| + petalinux-config --get-hw-description=/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/hardware_project --silentconfig | |
| INFO: Getting hardware description... | |
| INFO: Rename pynqz1.hdf to system.hdf | |
| [INFO] generating Kconfig for project | |
| [INFO] silentconfig project | |
| [INFO] sourcing bitbake | |
| [INFO] generating plnxtool conf | |
| [INFO] generating meta-plnx-generated layer | |
| [INFO] generating user layers | |
| [INFO] generating machine configuration | |
| [INFO] generating bbappends for project . This may take time ! | |
| [INFO] generating u-boot configuration files | |
| [INFO] generating kernel configuration files | |
| [INFO] generating kconfig for Rootfs | |
| [INFO] silentconfig rootfs | |
| [INFO] generating petalinux-user-image.bb | |
| + '[' -d /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/meta-user ']' | |
| + cp -rf /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/petalinux_bsp/meta-user/recipes-bsp /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/project-spec/meta-user | |
| + cd /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp | |
| + petalinux-package --force --bsp -p xilinx-pynqz1-2019.1 --output xilinx-pynqz1-2019.1.bsp | |
| /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1.bsp | |
| INFO: Target BSP "/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1.bsp" will contain the following projects | |
| INFO: PetaLinux project: /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1 | |
| INFO: Copying /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/config.project | |
| INFO: Copying /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/.petalinux | |
| INFO: Copying /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/.gitignore | |
| INFO: Copying /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/project-spec | |
| INFO: Copying /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1/components | |
| INFO: Creating BSP | |
| INFO: Generating package xilinx-pynqz1-2019.1.bsp... | |
| INFO: BSP is ready | |
| rm -rf /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| cd /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1 && petalinux-create -t project -s /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_bsp/xilinx-pynqz1-2019.1.bsp -n petalinux_project | |
| INFO: Create project: petalinux_project | |
| INFO: New project successfully created in /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| echo 'CONFIG_USER_LAYER_0="'/home/pcarr/PYNQ/sdbuild/boot/meta-pynq'"' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| echo 'CONFIG_SUBSYSTEM_ROOTFS_SD=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| echo 'CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| echo 'CONFIG_SUBSYSTEM_DEVICETREE_FLAGS="-@"' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| echo 'CONFIG_SUBSYSTEM_DTB_OVERLAY=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| echo 'CONFIG_SUBSYSTEM_FPGA_MANAGER=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/config | |
| # xrt only supports aarch64 in 2019.1; to remove in next release | |
| if [ arm = aarch64 ]; then echo 'CONFIG_xrt=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/rootfs_config ; echo 'CONFIG_xrt-dev=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/rootfs_config ; echo 'CONFIG_zocl=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/rootfs_config ; echo 'CONFIG_opencl-headers-dev=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/rootfs_config ; echo 'CONFIG_opencl-clhpp-dev=y' >> /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/project-spec/configs/rootfs_config ; fi | |
| petalinux-config --silentconfig -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] generating Kconfig for project | |
| [INFO] silentconfig project | |
| [INFO] sourcing bitbake | |
| [INFO] generating plnxtool conf | |
| [INFO] generating meta-plnx-generated layer | |
| [INFO] generating user layers | |
| [INFO] generating machine configuration | |
| [INFO] generating bbappends for project . This may take time ! | |
| [INFO] generating u-boot configuration files | |
| [INFO] generating kernel configuration files | |
| [INFO] generating kconfig for Rootfs | |
| [INFO] silentconfig rootfs | |
| [INFO] generating petalinux-user-image.bb | |
| [INFO] successfully configured project | |
| PYNQ_BOARDNAME=Pynq-Z1 petalinux-build -c device-tree -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] building device-tree | |
| [INFO] sourcing bitbake | |
| [INFO] generating user layers | |
| INFO: bitbake virtual/dtb | |
| Parsing recipes...done. | |
| Parsing of 2780 .bb files complete (0 cached, 2780 parsed). 3817 targets, 191 skipped, 0 masked, 0 errors. | |
| NOTE: Resolving any missing task queue dependencies | |
| Initialising tasks...done. | |
| Checking sstate mirror object availability...done. | |
| Sstate summary: Wanted 169 Found 140 Missed 58 Current 0 (82% match, 0% complete) | |
| NOTE: Executing SetScene Tasks | |
| NOTE: Running setscene task 1 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc-initial_8.2.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 2 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzop/lzop_1.03.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 3 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 4 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pkgconfig/pkgconfig_git.bb:do_populate_lic_setscene) | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gdbm-native-1.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe lzop-native-1.03-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 5 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe gdbm-native-1.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 6 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/dwarfsrcfiles/dwarfsrcfiles.bb:do_populate_lic_setscene) | |
| NOTE: recipe lzop-native-1.03-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 7 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pseudo/pseudo_git.bb:do_populate_lic_setscene) | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 8 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3-native_3.5.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe dwarfsrcfiles-native-1.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe unzip-native-1_6.0-r5: task do_populate_lic_setscene: Started | |
| NOTE: recipe python3-native-3.5.6-r1.0: task do_populate_lic_setscene: Started | |
| NOTE: recipe unzip-native-1_6.0-r5: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 9 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc_8.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe dwarfsrcfiles-native-1.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 10 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc_8.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe python3-native-3.5.6-r1.0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 11 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 12 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-gnome/gtk-doc/gtk-doc_1.29.bb:do_populate_lic_setscene) | |
| NOTE: recipe libgcc-8.2.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libgcc-8.2.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libgcc-8.2.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe bison-native-3.0.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 13 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/mpfr/mpfr_4.0.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe libgcc-8.2.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 14 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux-libc-headers/linux-libc-headers_4.18.bb:do_populate_lic_setscene) | |
| NOTE: recipe gtk-doc-native-1.29-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bison-native-3.0.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe gtk-doc-native-1.29-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 15 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 16 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe readline-native-7.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 18 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 19 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-native_2.4.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe readline-native-7.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 20 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe dbus-native-1.12.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe util-linux-native-2.32.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 22 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-cross-initial_8.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe util-linux-native-2.32.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe dbus-native-1.12.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 23 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/quilt/quilt-native_0.65.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 24 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_populate_lic_setscene) | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe quilt-native-0.65-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 25 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe quilt-native-0.65-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 26 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 27 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext-minimal-native_0.19.8.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe expat-native-2.2.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe expat-native-2.2.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 29 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-runtime_8.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 30 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-openembedded/meta-python/recipes-devtools/python/python3-cython_0.28.5.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 31 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux-libc-headers/linux-libc-headers_4.18.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe bzip2-native-1.0.6-r5: task do_populate_lic_setscene: Started | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe python3-cython-native-0.28.5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bzip2-native-1.0.6-r5: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 32 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 33 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/elfutils/elfutils_0.175.bb:do_populate_lic_setscene) | |
| NOTE: recipe python3-cython-native-0.28.5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 34 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_populate_lic_setscene) | |
| NOTE: recipe elfutils-native-0.175-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 35 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/rpm/rpm_4.14.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe xz-native-5.2.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe elfutils-native-0.175-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 36 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe xz-native-5.2.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 37 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pseudo/pseudo_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe rpm-native-1_4.14.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 38 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-runtime_8.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe rpm-native-1_4.14.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 39 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3-setuptools_40.0.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe lzo-native-2.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe lzo-native-2.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 40 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libyaml/libyaml_0.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe python3-setuptools-native-40.0.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 41 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/binutils/binutils-cross_2.31.bb:do_populate_lic_setscene) | |
| NOTE: recipe python3-setuptools-native-40.0.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 44 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/libarchive/libarchive_3.3.3.bb:do_populate_lic_setscene) | |
| NOTE: recipe libyaml-native-0.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 45 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc_8.2.bb:do_package_qa_setscene) | |
| NOTE: recipe libyaml-native-0.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 46 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-runtime_8.2.bb:do_package_qa_setscene) | |
| NOTE: recipe libarchive-native-3.3.3-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 47 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-openembedded/meta-python/recipes-devtools/python/python3-pyyaml_3.13.bb:do_populate_lic_setscene) | |
| NOTE: recipe libgcc-8.2.0-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libarchive-native-3.3.3-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 48 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libmpc/libmpc_1.1.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libgcc-8.2.0-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 49 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bc/bc_1.07.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe python3-pyyaml-native-3.13-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 50 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4-native_1.4.18.bb:do_populate_lic_setscene) | |
| NOTE: recipe python3-pyyaml-native-3.13-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe bc-native-1.07.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 51 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-cross_8.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 52 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-initial_2.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe m4-native-1.4.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bc-native-1.07.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe gcc-cross-arm-8.2.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 53 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_populate_lic_setscene) | |
| NOTE: recipe m4-native-1.4.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 54 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/nss/nss_3.39.bb:do_populate_lic_setscene) | |
| NOTE: recipe glibc-initial-2.28-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-cross-arm-8.2.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 55 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kern-tools/kern-tools-native_git.bb:do_populate_lic_setscene) | |
| NOTE: recipe glibc-initial-2.28-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 57 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc_2.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe nss-native-3.39-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe kern-tools-native-0.2+gitAUTOINC+d6529f86fc-r12: task do_populate_lic_setscene: Started | |
| NOTE: recipe nss-native-3.39-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 58 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe e2fsprogs-native-1.44.3-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe glibc-2.28-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe kern-tools-native-0.2+gitAUTOINC+d6529f86fc-r12: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 66 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/file/file_5.34.bb:do_populate_lic_setscene) | |
| NOTE: recipe e2fsprogs-native-1.44.3-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 67 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/texinfo-dummy-native/texinfo-dummy-native.bb:do_populate_lic_setscene) | |
| NOTE: recipe file-native-5.34-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe make-native-4.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe glibc-2.28-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 68 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc_2.28.bb:do_package_qa_setscene) | |
| NOTE: recipe file-native-5.34-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 69 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_populate_lic_setscene) | |
| NOTE: recipe make-native-4.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 70 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod-native_git.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 71 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux-libc-headers/linux-libc-headers_4.18.bb:do_package_qa_setscene) | |
| NOTE: recipe kmod-native-25+gitAUTOINC+aca4eca103-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe glibc-2.28-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe attr-native-2.4.47-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe kmod-native-25+gitAUTOINC+aca4eca103-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 72 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc_2.28.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 73 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/popt/popt_1.16.bb:do_populate_lic_setscene) | |
| NOTE: recipe glibc-2.28-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 74 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_populate_lic_setscene) | |
| NOTE: recipe attr-native-2.4.47-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 77 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-bsp/u-boot/u-boot-mkimage_2018.07.bb:do_populate_lic_setscene) | |
| NOTE: recipe popt-native-1.16-r3: task do_populate_lic_setscene: Started | |
| NOTE: recipe openssl-native-1.1.1a-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe glibc-2.28-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe popt-native-1.16-r3: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 78 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gperf/gperf_3.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe openssl-native-1.1.1a-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 79 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/unifdef/unifdef_2.11.bb:do_populate_lic_setscene) | |
| NOTE: recipe u-boot-mkimage-native-1_2018.07-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe u-boot-mkimage-native-1_2018.07-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 80 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf/autoconf_2.69.bb:do_populate_lic_setscene) | |
| NOTE: recipe gperf-native-3.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe unifdef-native-2.11-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gperf-native-3.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe glibc-2.28-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 81 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_populate_lic_setscene) | |
| NOTE: recipe unifdef-native-2.11-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 82 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/nspr/nspr_4.19.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 84 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/automake/automake_1.16.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe autoconf-native-2.69-r11: task do_populate_lic_setscene: Started | |
| NOTE: recipe autoconf-native-2.69-r11: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 85 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe automake-native-1.16.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe ncurses-native-6.1+20180630-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe nspr-native-4.19-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe automake-native-1.16.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 86 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gnu-config/gnu-config_git.bb:do_populate_lic_setscene) | |
| NOTE: recipe nspr-native-4.19-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe ncurses-native-6.1+20180630-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe flex-native-2.6.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 88 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 89 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/dtc/dtc_1.4.7.bb:do_populate_lic_setscene) | |
| NOTE: recipe flex-native-2.6.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 91 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-bsp/u-boot/u-boot-mkimage_2018.07.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe dtc-native-1.4.7-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 93 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bc/bc_1.07.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe u-boot-mkimage-native-1_2018.07-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 94 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzop/lzop_1.03.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe dtc-native-1.4.7-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 95 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-openembedded/meta-python/recipes-devtools/python/python3-pyyaml_3.13.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe u-boot-mkimage-native-1_2018.07-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 96 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod-native_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bc-native-1.07.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe lzop-native-1.03-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe python3-pyyaml-native-3.13-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe kmod-native-25+gitAUTOINC+aca4eca103-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bc-native-1.07.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 97 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/dtc/dtc_1.4.7.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python3-pyyaml-native-3.13-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 98 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libyaml/libyaml_0.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe lzop-native-1.03-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 99 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-openembedded/meta-python/recipes-devtools/python/python3-cython_0.28.5.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe kmod-native-25+gitAUTOINC+aca4eca103-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 100 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-gnome/gtk-doc/gtk-doc_1.29.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python3-cython-native-0.28.5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe dtc-native-1.4.7-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libyaml-native-0.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gtk-doc-native-1.29-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libyaml-native-0.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 101 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kern-tools/kern-tools-native_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe dtc-native-1.4.7-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 102 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe python3-cython-native-0.28.5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 103 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3-setuptools_40.0.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gtk-doc-native-1.29-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe kern-tools-native-0.2+gitAUTOINC+d6529f86fc-r12: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 106 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-runtime_8.2.bb:do_packagedata_setscene) | |
| NOTE: recipe kern-tools-native-0.2+gitAUTOINC+d6529f86fc-r12: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 107 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-runtime_8.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python3-setuptools-native-40.0.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe db-native-1_5.3.28-r1: task do_populate_lic_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe db-native-1_5.3.28-r1: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe python3-setuptools-native-40.0.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 108 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 110 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc_8.2.bb:do_packagedata_setscene) | |
| NOTE: recipe unzip-native-1_6.0-r5: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libgcc-8.2.0-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe unzip-native-1_6.0-r5: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libgcc-8.2.0-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 112 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc_2.28.bb:do_packagedata_setscene) | |
| NOTE: recipe glibc-2.28-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gcc-runtime-8.2.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 113 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc_8.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glibc-2.28-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe libgcc-8.2.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 115 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux-libc-headers/linux-libc-headers_4.18.bb:do_packagedata_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libgcc-8.2.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 116 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-cross_8.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 118 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/rpm/rpm_4.14.2.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 119 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/dwarfsrcfiles/dwarfsrcfiles.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gcc-cross-arm-8.2.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe rpm-native-1_4.14.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe dwarfsrcfiles-native-1.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe dwarfsrcfiles-native-1.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe rpm-native-1_4.14.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 120 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/popt/popt_1.16.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 121 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3-native_3.5.6.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 122 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/file/file_5.34.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python3-native-3.5.6-r1.0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe popt-native-1.16-r3: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe file-native-5.34-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe popt-native-1.16-r3: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 123 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe file-native-5.34-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 124 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/nss/nss_3.39.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe db-native-1_5.3.28-r1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe nss-native-3.39-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gcc-cross-arm-8.2.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 126 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc_2.28.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe db-native-1_5.3.28-r1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 127 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/libarchive/libarchive_3.3.3.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glibc-2.28-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libarchive-native-3.3.3-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libarchive-native-3.3.3-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 128 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe dbus-native-1.12.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe nss-native-3.39-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 129 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/nspr/nspr_4.19.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python3-native-3.5.6-r1.0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 130 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe dbus-native-1.12.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 131 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe readline-native-7.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe nspr-native-4.19-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe readline-native-7.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 132 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gdbm-native-1.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe glibc-2.28-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 133 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gdbm-native-1.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 135 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gperf/gperf_3.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bzip2-native-1.0.6-r5: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe openssl-native-1.1.1a-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gperf-native-3.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gperf-native-3.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 136 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bzip2-native-1.0.6-r5: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 137 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/elfutils/elfutils_0.175.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe openssl-native-1.1.1a-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 138 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe expat-native-2.2.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe elfutils-native-0.175-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe expat-native-2.2.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 139 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-initial_2.28.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe glibc-initial-2.28-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 140 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe elfutils-native-0.175-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe glibc-initial-2.28-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 142 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux-libc-headers/linux-libc-headers_4.18.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 143 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe nspr-native-4.19-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 144 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc-initial_8.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe e2fsprogs-native-1.44.3-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe make-native-4.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe linux-libc-headers-4.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 145 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/unifdef/unifdef_2.11.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe make-native-4.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 146 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-cross-initial_8.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe unifdef-native-2.11-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe e2fsprogs-native-1.44.3-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 147 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 148 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe unifdef-native-2.11-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe attr-native-2.4.47-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-linux-native-2.32.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe attr-native-2.4.47-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 150 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libmpc/libmpc_1.1.0.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 151 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/binutils/binutils-cross_2.31.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 152 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/mpfr/mpfr_4.0.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe util-linux-native-2.32.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 153 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 154 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 155 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe lzo-native-2.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe ncurses-native-6.1+20180630-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 156 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe lzo-native-2.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 157 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 158 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe ncurses-native-6.1+20180630-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 159 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pkgconfig/pkgconfig_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bison-native-3.0.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bison-native-3.0.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 160 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 161 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe flex-native-2.6.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe xz-native-5.2.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe flex-native-2.6.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe xz-native-5.2.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 162 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-native_2.4.6.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 163 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext-minimal-native_0.19.8.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 164 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/automake/automake_1.16.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe automake-native-1.16.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe automake-native-1.16.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 165 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf/autoconf_2.69.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe autoconf-native-2.69-r11: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe autoconf-native-2.69-r11: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 166 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4-native_1.4.18.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe m4-native-1.4.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe m4-native-1.4.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 167 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/texinfo-dummy-native/texinfo-dummy-native.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 168 of 169 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gnu-config/gnu-config_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 169 of 169 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/quilt/quilt-native_0.65.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe quilt-native-0.65-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe quilt-native-0.65-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Executing RunQueue Tasks | |
| NOTE: Running task 1 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-source_8.2.bb:do_rm_work) | |
| NOTE: Running task 2 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_rm_work) | |
| NOTE: Running task 12 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/quilt/quilt-native_0.65.bb:do_rm_work) | |
| NOTE: Running task 22 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/texinfo-dummy-native/texinfo-dummy-native.bb:do_rm_work) | |
| NOTE: recipe gcc-source-8.2.0-8.2.0-r0: task do_rm_work: Started | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_rm_work: Started | |
| NOTE: recipe quilt-native-0.65-r0: task do_rm_work: Started | |
| NOTE: recipe gcc-source-8.2.0-8.2.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 32 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gnu-config/gnu-config_git.bb:do_rm_work) | |
| NOTE: recipe texinfo-dummy-native-1.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 42 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4-native_1.4.18.bb:do_rm_work) | |
| NOTE: recipe quilt-native-0.65-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 52 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf/autoconf_2.69.bb:do_rm_work) | |
| NOTE: recipe m4-native-1.4.18-r0: task do_rm_work: Started | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_rm_work: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_rm_work: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 62 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/automake/automake_1.16.1.bb:do_rm_work) | |
| NOTE: recipe gnu-config-native-20180713+gitAUTOINC+30d53fc428-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 72 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-native_2.4.6.bb:do_rm_work) | |
| NOTE: recipe m4-native-1.4.18-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 82 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext-minimal-native_0.19.8.1.bb:do_rm_work) | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_rm_work: Started | |
| NOTE: recipe autoconf-native-2.69-r11: task do_rm_work: Started | |
| NOTE: recipe automake-native-1.16.1-r0: task do_rm_work: Started | |
| NOTE: recipe libtool-native-2.4.6-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 92 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_rm_work) | |
| NOTE: recipe automake-native-1.16.1-r0: task do_rm_work: Succeeded | |
| NOTE: recipe autoconf-native-2.69-r11: task do_rm_work: Succeeded | |
| NOTE: Running task 102 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_rm_work) | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_rm_work: Started | |
| NOTE: Running task 112 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_rm_work) | |
| NOTE: recipe gettext-minimal-native-0.19.8.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 122 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_rm_work) | |
| NOTE: recipe xz-native-5.2.4-r0: task do_rm_work: Started | |
| NOTE: recipe xz-native-5.2.4-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 132 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_rm_work) | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_rm_work: Started | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_rm_work: Started | |
| NOTE: recipe flex-native-2.6.0-r0: task do_rm_work: Started | |
| NOTE: recipe gmp-native-6.1.2-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 142 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/mpfr/mpfr_4.0.1.bb:do_rm_work) | |
| NOTE: recipe zlib-native-1.2.11-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 152 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_rm_work) | |
| NOTE: recipe flex-native-2.6.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 162 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/binutils/binutils-cross_2.31.bb:do_rm_work) | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_rm_work: Started | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_rm_work: Started | |
| NOTE: recipe bison-native-3.0.4-r0: task do_rm_work: Started | |
| NOTE: recipe autoconf-archive-native-2018.03.13-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 172 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libmpc/libmpc_1.1.0.bb:do_rm_work) | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_rm_work: Started | |
| NOTE: recipe mpfr-native-4.0.1-r0: task do_rm_work: Succeeded | |
| NOTE: recipe bison-native-3.0.4-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 182 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pkgconfig/pkgconfig_git.bb:do_rm_work) | |
| NOTE: Running task 199 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/gcc-cross-initial_8.2.bb:do_rm_work) | |
| NOTE: recipe binutils-cross-arm-2.31-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 209 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_rm_work) | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_rm_work: Started | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_rm_work: Started | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_rm_work: Started | |
| NOTE: recipe libmpc-native-1.1.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 219 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_rm_work) | |
| NOTE: recipe gcc-cross-initial-arm-8.2.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 229 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/pseudo/pseudo_git.bb:do_rm_work) | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_rm_work: Started | |
| NOTE: recipe pkgconfig-native-0.29.2+gitAUTOINC+edf8e6f0ea-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 238 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/gcc/libgcc-initial_8.2.bb:do_rm_work) | |
| NOTE: recipe attr-native-2.4.47-r0: task do_rm_work: Started | |
| NOTE: recipe sqlite3-native-3_3.23.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 248 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/unifdef/unifdef_2.11.bb:do_rm_work) | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_rm_work: Started | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_rm_work: Started | |
| NOTE: recipe attr-native-2.4.47-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 267 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_rm_work) | |
| NOTE: recipe pseudo-native-1.9.0+gitAUTOINC+6294b344e5-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 279 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-initial_2.28.bb:do_rm_work) | |
| NOTE: recipe libgcc-initial-8.2.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 289 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gperf/gperf_3.1.bb:do_rm_work) | |
| NOTE: recipe unifdef-native-2.11-r0: task do_rm_work: Started | |
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| NOTE: Running task 310 of 729 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_rm_work) | |
| NOTE: recipe make-native-4.2.1-r0: task do_rm_work: Started | |
| NOTE: recipe glibc-initial-2.28-r0: task do_rm_work: Started | |
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| NOTE: Running task 675 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_create_yaml) | |
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| NOTE: Running task 687 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_unpack) | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_unpack: Started | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_unpack: Succeeded | |
| NOTE: Running task 688 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_patch) | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_patch: Started | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_patch: Succeeded | |
| NOTE: Running task 689 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_configure) | |
| NOTE: recipe external-hdf-1.0-r0: task do_package_write_rpm: Succeeded | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_configure: Started | |
| NOTE: Running task 690 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/hdf/external-hdf.bb:do_rm_work) | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_configure: Succeeded | |
| NOTE: Running task 691 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_compile) | |
| NOTE: recipe external-hdf-1.0-r0: task do_rm_work: Started | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_compile: Started | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_compile: Succeeded | |
| NOTE: Running task 692 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_install) | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_install: Started | |
| NOTE: recipe external-hdf-1.0-r0: task do_rm_work: Succeeded | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_install: Succeeded | |
| NOTE: Running task 693 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/depmodwrapper-cross_1.0.bb:do_populate_sysroot) | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_populate_sysroot: Started | |
| NOTE: recipe depmodwrapper-cross-1.0-r0: task do_populate_sysroot: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_fetch: Succeeded | |
| NOTE: Running task 694 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_prepare_recipe_sysroot) | |
| NOTE: Running task 695 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_unpack) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_unpack: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_prepare_recipe_sysroot: Succeeded | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_configure: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_unpack: Succeeded | |
| NOTE: Running task 696 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_checkout) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_checkout: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_checkout: Succeeded | |
| NOTE: Running task 697 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_validate_branches) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_validate_branches: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_validate_branches: Succeeded | |
| NOTE: Running task 698 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_metadata) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_metadata: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_metadata: Succeeded | |
| NOTE: Running task 699 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_version_sanity_check) | |
| NOTE: Running task 700 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_patch) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_patch: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_version_sanity_check: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_version_sanity_check: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_patch: Succeeded | |
| NOTE: Running task 701 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_configme) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_configme: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_configme: Succeeded | |
| NOTE: Running task 702 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_configure) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_configure: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_configure: Succeeded | |
| NOTE: Running task 703 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_compile) | |
| NOTE: Running task 704 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_configcheck) | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_compile: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_compile: Succeeded | |
| NOTE: Running task 705 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_install) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_configcheck: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_install: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_install: Succeeded | |
| NOTE: Running task 706 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_package) | |
| NOTE: Running task 707 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_populate_sysroot) | |
| NOTE: Running task 708 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_deploy) | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_populate_sysroot: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_deploy: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_deploy: Succeeded | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_populate_sysroot: Succeeded | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package: Succeeded | |
| NOTE: Running task 709 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_packagedata) | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_packagedata: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_packagedata: Succeeded | |
| NOTE: Running task 710 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_package_qa) | |
| NOTE: Running task 711 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_package_write_rpm) | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_qa: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_write_rpm: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_qa: Succeeded | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_write_rpm: Succeeded | |
| NOTE: Running task 712 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_rm_work) | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_rm_work: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_rm_work: Succeeded | |
| NOTE: Running noexec task 713 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_rm_work_all) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_configcheck: Succeeded | |
| NOTE: Running task 714 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_compile) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_compile: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_compile: Succeeded | |
| NOTE: Running task 715 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_assemble_fitimage) | |
| NOTE: Running task 716 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_kernel_link_images) | |
| NOTE: Running task 717 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_shared_workdir) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_assemble_fitimage: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_link_images: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_kernel_link_images: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_shared_workdir: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_shared_workdir: Succeeded | |
| NOTE: Running task 718 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_compile_kernelmodules) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_assemble_fitimage: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_compile_kernelmodules: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_compile_kernelmodules: Succeeded | |
| NOTE: Running task 719 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_strip) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_strip: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_strip: Succeeded | |
| NOTE: Running task 720 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_sizecheck) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_sizecheck: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_sizecheck: Succeeded | |
| NOTE: Running task 721 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_install) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_install: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_install: Succeeded | |
| NOTE: Running task 722 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_bundle_initramfs) | |
| NOTE: Running task 723 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_package) | |
| NOTE: Running task 724 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_populate_sysroot) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_bundle_initramfs: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_bundle_initramfs: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_populate_sysroot: Started | |
| NOTE: Running task 725 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_assemble_fitimage_initramfs) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_populate_sysroot: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_assemble_fitimage_initramfs: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_assemble_fitimage_initramfs: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package: Succeeded | |
| NOTE: Running task 726 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_packagedata) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_packagedata: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_packagedata: Succeeded | |
| NOTE: Running task 727 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_package_write_rpm) | |
| NOTE: Running task 728 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_deploy) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_deploy: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package_write_rpm: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_deploy: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package_write_rpm: Succeeded | |
| NOTE: Running noexec task 729 of 729 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_build) | |
| NOTE: Tasks Summary: Attempted 729 tasks of which 596 didn't need to be rerun and all succeeded. | |
| INFO: Copying Images from deploy to images | |
| INFO: Creating images/linux directory | |
| NOTE: Failed to copy built images to tftp dir: /tftpboot | |
| [INFO] successfully built device-tree | |
| cp /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/images/linux/system.dtb /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/system.dtb | |
| PYNQ_BOARDNAME=Pynq-Z1 petalinux-build -c kernel -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] building kernel | |
| [INFO] sourcing bitbake | |
| [INFO] generating user layers | |
| INFO: bitbake virtual/kernel | |
| Loading cache...done. | |
| Loaded 3813 entries from dependency cache. | |
| Parsing recipes...done. | |
| Parsing of 2780 .bb files complete (2778 cached, 2 parsed). 3817 targets, 191 skipped, 0 masked, 0 errors. | |
| NOTE: Resolving any missing task queue dependencies | |
| Initialising tasks...done. | |
| Checking sstate mirror object availability...done. | |
| Sstate summary: Wanted 14 Found 4 Missed 20 Current 142 (28% match, 93% complete) | |
| NOTE: Executing SetScene Tasks | |
| NOTE: Running setscene task 144 of 156 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_package_write_rpm_setscene) | |
| NOTE: Running setscene task 148 of 156 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/hdf/external-hdf.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe external-hdf-1.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe external-hdf-1.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe device-tree-xilinx+gitAUTOINC+73e546e312-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Executing RunQueue Tasks | |
| NOTE: Running task 314 of 706 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_populate_lic) | |
| NOTE: Running noexec task 603 of 706 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_rm_work_all) | |
| NOTE: Running task 694 of 706 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_package_qa) | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_populate_lic: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_populate_lic: Succeeded | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package_qa: Started | |
| NOTE: recipe linux-xlnx-4.19-xilinx-v2019.1+gitAUTOINC+9811303824-r0: task do_package_qa: Succeeded | |
| NOTE: Running noexec task 706 of 706 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb:do_build) | |
| NOTE: Tasks Summary: Attempted 706 tasks of which 702 didn't need to be rerun and all succeeded. | |
| INFO: Copying Images from deploy to images | |
| NOTE: Failed to copy built images to tftp dir: /tftpboot | |
| [INFO] successfully built kernel | |
| cp /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/images/linux/zImage /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/zImage | |
| mkdir -p /home/pcarr/PYNQ/sdbuild/output/boot/Pynq-Z1 | |
| cd /home/pcarr/PYNQ/sdbuild/output/boot/Pynq-Z1 && mkimage -f /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/image.its /home/pcarr/PYNQ/sdbuild/output/boot/Pynq-Z1/image.ub | |
| FIT description: U-Boot fitImage for PYNQ arm kernel | |
| Created: Fri Nov 1 16:41:31 2019 | |
| Image 0 (kernel@0) | |
| Description: Linux Kernel | |
| Created: Fri Nov 1 16:41:31 2019 | |
| Type: Kernel Image | |
| Compression: uncompressed | |
| Data Size: 4752880 Bytes = 4641.48 kB = 4.53 MB | |
| Architecture: ARM | |
| OS: Linux | |
| Load Address: 0x00080000 | |
| Entry Point: 0x00080000 | |
| Hash algo: sha1 | |
| Hash value: 347732c1de28d9de5ca33314a80ceb184fb8f8fd | |
| Image 1 (fdt@0) | |
| Description: Flattened Device Tree blob | |
| Created: Fri Nov 1 16:41:31 2019 | |
| Type: Flat Device Tree | |
| Compression: uncompressed | |
| Data Size: 16954 Bytes = 16.56 kB = 0.02 MB | |
| Architecture: ARM | |
| Hash algo: sha1 | |
| Hash value: bb9aceb1aa0ef7d7cf99592ca10073bec7fcd84e | |
| Default Configuration: 'conf@1' | |
| Configuration 0 (conf@1) | |
| Description: Boot Linux kernel with FDT blob | |
| Kernel: kernel@0 | |
| FDT: fdt@0 | |
| PYNQ_BOARDNAME=Pynq-Z1 petalinux-build -c u-boot -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] building u-boot | |
| [INFO] sourcing bitbake | |
| [INFO] generating user layers | |
| INFO: bitbake virtual/bootloader | |
| Loading cache...done. | |
| Loaded 3813 entries from dependency cache. | |
| Parsing recipes...done. | |
| Parsing of 2780 .bb files complete (2778 cached, 2 parsed). 3817 targets, 191 skipped, 0 masked, 0 errors. | |
| NOTE: Resolving any missing task queue dependencies | |
| Initialising tasks...done. | |
| Checking sstate mirror object availability...done. | |
| Sstate summary: Wanted 23 Found 8 Missed 30 Current 159 (34% match, 91% complete) | |
| NOTE: Executing SetScene Tasks | |
| NOTE: Running setscene task 162 of 182 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python-native_2.7.15.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 164 of 182 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 168 of 182 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/swig/swig_3.0.12.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 178 of 182 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/swig/swig_3.0.12.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpcre-native-8.42-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe swig-native-3.0.12-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 179 of 182 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python-native_2.7.15.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe swig-native-3.0.12-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpcre-native-8.42-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe swig-native-3.0.12-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe swig-native-3.0.12-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 182 of 182 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpcre-native-8.42-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libpcre-native-8.42-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Executing RunQueue Tasks | |
| NOTE: Running task 718 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_fetch) | |
| NOTE: Running task 728 of 775 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_rm_work) | |
| NOTE: Running task 738 of 775 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/swig/swig_3.0.12.bb:do_rm_work) | |
| NOTE: Running task 748 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python-native_2.7.15.bb:do_rm_work) | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_rm_work: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_fetch: Started | |
| NOTE: recipe swig-native-3.0.12-r0: task do_rm_work: Started | |
| NOTE: recipe python-native-2.7.15-r1.1: task do_rm_work: Succeeded | |
| NOTE: recipe libpcre-native-8.42-r0: task do_rm_work: Started | |
| NOTE: recipe swig-native-3.0.12-r0: task do_rm_work: Succeeded | |
| NOTE: recipe libpcre-native-8.42-r0: task do_rm_work: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_fetch: Succeeded | |
| NOTE: Running task 759 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_prepare_recipe_sysroot) | |
| NOTE: Running task 760 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_unpack) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_unpack: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_prepare_recipe_sysroot: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_unpack: Succeeded | |
| NOTE: Running task 761 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_patch) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_patch: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_patch: Succeeded | |
| NOTE: Running task 762 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_populate_lic) | |
| NOTE: Running task 763 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_configure) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_populate_lic: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_configure: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_populate_lic: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_configure: Succeeded | |
| NOTE: Running task 764 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_compile) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_compile: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_compile: Succeeded | |
| NOTE: Running task 765 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_create_extlinux_config) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_create_extlinux_config: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_create_extlinux_config: Succeeded | |
| NOTE: Running task 766 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_deploy) | |
| NOTE: Running task 767 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_install) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_deploy: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_deploy: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_install: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_install: Succeeded | |
| NOTE: Running task 768 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_populate_sysroot) | |
| NOTE: Running task 769 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_package) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_populate_sysroot: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_populate_sysroot: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package: Succeeded | |
| NOTE: Running task 770 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_packagedata) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_packagedata: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_packagedata: Succeeded | |
| NOTE: Running task 771 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_package_qa) | |
| NOTE: Running task 772 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_package_write_rpm) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package_qa: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package_write_rpm: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package_qa: Succeeded | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_package_write_rpm: Succeeded | |
| NOTE: Running task 773 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_rm_work) | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_rm_work: Started | |
| NOTE: recipe u-boot-xlnx-v2019.01-xilinx-v2019.1+gitAUTOINC+d895ac5e94-r0: task do_rm_work: Succeeded | |
| NOTE: Running noexec task 774 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_rm_work_all) | |
| NOTE: Running noexec task 775 of 775 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb:do_build) | |
| NOTE: Tasks Summary: Attempted 775 tasks of which 754 didn't need to be rerun and all succeeded. | |
| INFO: Copying Images from deploy to images | |
| NOTE: Failed to copy built images to tftp dir: /tftpboot | |
| [INFO] successfully built u-boot | |
| PYNQ_BOARDNAME=Pynq-Z1 petalinux-build -c bootloader -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] building bootloader | |
| [INFO] sourcing bitbake | |
| [INFO] generating user layers | |
| INFO: bitbake virtual/fsbl | |
| Loading cache...done. | |
| Loaded 3813 entries from dependency cache. | |
| Parsing recipes...done. | |
| Parsing of 2780 .bb files complete (2778 cached, 2 parsed). 3817 targets, 191 skipped, 0 masked, 0 errors. | |
| NOTE: Resolving any missing task queue dependencies | |
| Initialising tasks...done. | |
| Checking sstate mirror object availability...done. | |
| Sstate summary: Wanted 16 Found 1 Missed 30 Current 132 (6% match, 89% complete) | |
| NOTE: Executing SetScene Tasks | |
| NOTE: Executing RunQueue Tasks | |
| NOTE: Running task 592 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_fetch) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_fetch: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_fetch: Succeeded | |
| NOTE: Running task 608 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_prepare_recipe_sysroot) | |
| NOTE: Running task 609 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_unpack) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_unpack: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_prepare_recipe_sysroot: Succeeded | |
| NOTE: Running task 610 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_create_yaml) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_create_yaml: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_create_yaml: Succeeded | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_unpack: Succeeded | |
| NOTE: Running task 611 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_patch) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_patch: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_patch: Succeeded | |
| NOTE: Running task 612 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_populate_lic) | |
| NOTE: Running task 613 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_configure) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_populate_lic: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_configure: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_populate_lic: Succeeded | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_configure: Succeeded | |
| NOTE: Running task 614 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_compile) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_compile: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_compile: Succeeded | |
| NOTE: Running task 615 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_deploy) | |
| NOTE: Running task 616 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_install) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_deploy: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_deploy: Succeeded | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_install: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_install: Succeeded | |
| NOTE: Running task 617 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_package) | |
| NOTE: Running task 618 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_populate_sysroot) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_populate_sysroot: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_populate_sysroot: Succeeded | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package: Succeeded | |
| NOTE: Running task 619 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_packagedata) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_packagedata: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_packagedata: Succeeded | |
| NOTE: Running task 620 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_package_qa) | |
| NOTE: Running task 621 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_package_write_rpm) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package_qa: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package_write_rpm: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package_qa: Succeeded | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_package_write_rpm: Succeeded | |
| NOTE: Running task 622 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_rm_work) | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_rm_work: Started | |
| NOTE: recipe fsbl-2019.1+gitAUTOINC+26c14d9861-r0: task do_rm_work: Succeeded | |
| NOTE: Running noexec task 623 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_rm_work_all) | |
| NOTE: Running noexec task 624 of 624 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/meta-xilinx-tools/recipes-bsp/fsbl/fsbl_git.bb:do_build) | |
| NOTE: Tasks Summary: Attempted 624 tasks of which 606 didn't need to be rerun and all succeeded. | |
| INFO: Copying Images from deploy to images | |
| NOTE: Failed to copy built images to tftp dir: /tftpboot | |
| [INFO] successfully built bootloader | |
| cd /home/pcarr/PYNQ/sdbuild/output/boot/Pynq-Z1 && petalinux-package --boot --fpga /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/base/base.bit --u-boot -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project --force | |
| WARNING: Fpga Manager enabled, skipping bitstream to pack into BOOT.BIN | |
| INFO: File in BOOT BIN: "/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/images/linux/zynq_fsbl.elf" | |
| INFO: File in BOOT BIN: "/home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/images/linux/u-boot.elf" | |
| INFO: Generating Zynq binary package BOOT.BIN... | |
| ****** Xilinx Bootgen v2019.1 | |
| **** Build date : May 11 2019-11:15:10 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| INFO: Binary is ready. | |
| WARNING: Unable to access the TFTPBOOT folder /tftpboot!!! | |
| WARNING: Skip file copy to TFTPBOOT folder!!! | |
| cp -f /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/images/linux/BOOT.BIN /home/pcarr/PYNQ/sdbuild/output/boot/Pynq-Z1 | |
| git clone ../ /home/pcarr/PYNQ/sdbuild/build/PYNQ | |
| Cloning into '/home/pcarr/PYNQ/sdbuild/build/PYNQ'... | |
| done. | |
| cd /home/pcarr/PYNQ/sdbuild/build/PYNQ && git submodule init && git submodule update | |
| Submodule 'pynq/lib/_pynq/embeddedsw' (https://github.com/Xilinx/embeddedsw.git) registered for path 'pynq/lib/_pynq/embeddedsw' | |
| Cloning into 'pynq/lib/_pynq/embeddedsw'... | |
| Submodule path 'pynq/lib/_pynq/embeddedsw': checked out '324e7b58ecc9ea06a929fb545d73565cafb9989a' | |
| cd /home/pcarr/PYNQ/sdbuild/build/PYNQ && git fetch origin && git checkout 3f634506e4d428cb07bb5a57c1d95cab0c803d20 | |
| Note: checking out '3f634506e4d428cb07bb5a57c1d95cab0c803d20'. | |
| You are in 'detached HEAD' state. You can look around, make experimental | |
| changes and commit them, and you can discard any commits you make in this | |
| state without impacting any branches by performing another checkout. | |
| If you want to create a new branch to retain commits you create, you may | |
| do so (now or later) by using -b with the checkout command again. Example: | |
| git checkout -b <new-branch-name> | |
| HEAD is now at 3f63450... small fix to setup_host.sh (#957) | |
| cp -f /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/build/tmp/deploy/images/*/modules--*.tgz /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/build/tmp/deploy/images/modules-plnx_arm.tgz | |
| PYNQ_BOARDNAME=Pynq-Z1 petalinux-build -c kernel-devsrc -p /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project | |
| [INFO] building kernel-devsrc | |
| [INFO] sourcing bitbake | |
| [INFO] generating user layers | |
| INFO: bitbake kernel-devsrc | |
| Loading cache...done. | |
| Loaded 3813 entries from dependency cache. | |
| Parsing recipes...done. | |
| Parsing of 2780 .bb files complete (2778 cached, 2 parsed). 3817 targets, 191 skipped, 0 masked, 0 errors. | |
| NOTE: Resolving any missing task queue dependencies | |
| Initialising tasks...done. | |
| Checking sstate mirror object availability...done. | |
| Sstate summary: Wanted 513 Found 405 Missed 216 Current 163 (78% match, 84% complete) | |
| NOTE: Executing SetScene Tasks | |
| NOTE: Running setscene task 164 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_package_write_rpm_setscene) | |
| NOTE: Running setscene task 166 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 167 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 169 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_populate_lic_setscene: Started | |
| NOTE: recipe grep-3.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 170 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 171 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe grep-3.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 172 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe bison-3.0.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 173 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/which/which_2.21.bb:do_populate_lic_setscene) | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 174 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe libpam-1.3.0-r5: task do_populate_lic_setscene: Started | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 175 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_package_qa_setscene) | |
| NOTE: recipe which-2.21-r3: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpam-1.3.0-r5: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe bison-3.0.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 176 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzcode/tzcode-native_2018g.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 177 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_populate_lic_setscene) | |
| NOTE: recipe which-2.21-r3: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 178 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe attr-2.4.47-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe tzcode-native-2018g-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe eudev-3.2.5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe tzcode-native-2018g-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 179 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_package_qa_setscene) | |
| NOTE: recipe make-4.2.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe attr-2.4.47-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 181 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_populate_lic_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 182 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpcre-8.42-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe make-4.2.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 184 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe tzdata-2018g-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpcre-8.42-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 185 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_package_qa_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 186 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_populate_lic_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe eudev-3.2.5-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe acl-2.2.52-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 187 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 188 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 189 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_populate_lic_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 190 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/btrfs-tools/btrfs-tools_4.17.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bash-4.4.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 191 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 192 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 193 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_package_qa_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 194 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4_1.4.18.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe shadow-4.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 195 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_package_qa_setscene) | |
| NOTE: recipe m4-1.4.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 196 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe python3-3.5.6-r1.0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 197 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe m4-1.4.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 198 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/btrfs-tools/btrfs-tools_4.17.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libcap-2.25-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe attr-2.4.47-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe zlib-1.2.11-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 199 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_package_qa_setscene) | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 200 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe attr-2.4.47-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 201 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_populate_lic_setscene) | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 203 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_package_qa_setscene) | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 204 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_package_qa_setscene) | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 205 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_package_qa_setscene: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 206 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/btrfs-tools/btrfs-tools_4.17.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 207 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_package_qa_setscene) | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 208 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_populate_lic_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 209 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_package_qa_setscene) | |
| NOTE: recipe readline-7.0-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe readline-7.0-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 210 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_package_qa_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 211 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe cracklib-2.9.5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 212 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/btrfs-tools/btrfs-tools_4.17.1.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 213 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 214 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 215 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_package_qa_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 216 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shadow-native-4.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe shadow-native-4.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 217 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe shadow-4.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe xz-5.2.4-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe diffutils-3.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 218 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_package_qa_setscene) | |
| NOTE: recipe xz-5.2.4-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 219 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_package_qa_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 220 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 221 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe lzo-2.10-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe unzip-1_6.0-r5: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_package_qa_setscene: Started | |
| NOTE: recipe lzo-2.10-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 222 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_package_qa_setscene) | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 223 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_populate_lic_setscene) | |
| NOTE: recipe unzip-1_6.0-r5: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 224 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_populate_lic_setscene) | |
| NOTE: recipe db-1_5.3.28-r1: task do_package_qa_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 225 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe db-1_5.3.28-r1: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 226 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_package_qa_setscene) | |
| NOTE: recipe expat-2.2.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 227 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe grep-3.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 228 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe initscripts-1.0-r155: task do_populate_lic_setscene: Started | |
| NOTE: recipe grep-3.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 229 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe initscripts-1.0-r155: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 230 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_package_qa_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 231 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_package_qa_setscene) | |
| NOTE: recipe shadow-4.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe opkg-utils-native-0.3.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 232 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe gdbm-1.18-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe opkg-utils-native-0.3.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 233 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_populate_lic_setscene) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 235 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe procps-3.3.15-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gdbm-1.18-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 236 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 237 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_populate_lic_setscene) | |
| NOTE: recipe procps-3.3.15-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 238 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_package_qa_setscene) | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe acl-2.2.52-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 239 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 240 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext_0.19.8.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 241 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_package_qa_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe bash-completion-2.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 242 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 243 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 245 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 246 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_package_qa_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 247 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_package_qa_setscene) | |
| NOTE: recipe readline-7.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 248 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_populate_lic_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe readline-7.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 249 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu_3.0.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 250 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_package_qa_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 251 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gawk-4.2.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 252 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxcb-1.13-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 253 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 254 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxcb-1.13-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 255 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_package_qa_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe bash-4.4.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 256 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_package_qa_setscene) | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 257 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/debianutils/debianutils_4.8.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 258 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_package_qa_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 259 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl-native_5.24.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 260 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe debianutils-native-4.8.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe perl-native-5.24.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe perl-native-5.24.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 261 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 262 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_package_qa_setscene) | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 263 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_package_qa_setscene) | |
| NOTE: recipe debianutils-native-4.8.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 264 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/pixman_0.34.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe dbus-1.12.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe diffutils-3.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe make-4.2.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe make-4.2.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 265 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 266 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe dbus-1.12.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 267 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_package_qa_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 268 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe make-4.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe make-4.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 271 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 272 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 273 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 274 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_package_qa_setscene) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libxcb-1.13-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 275 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 276 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxcb-1.13-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 277 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/alsa/alsa-lib_1.1.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 278 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_package_qa_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe flex-2.6.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_package_qa_setscene: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 279 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe initscripts-1.0-r155: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 280 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/which/which_2.21.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: Running setscene task 281 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe flex-2.6.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 282 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_package_qa_setscene) | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 283 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe which-2.21-r3: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_populate_lic_setscene: Started | |
| NOTE: recipe unzip-1_6.0-r5: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe which-2.21-r3: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 284 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_populate_lic_setscene) | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 285 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxcb-1.13-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe unzip-1_6.0-r5: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 286 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_package_qa_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe libxcb-1.13-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 287 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 288 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe coreutils-8.30-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe coreutils-8.30-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 289 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_package_qa_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 290 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 291 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 292 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 293 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe xorgproto-2018.4-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 295 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ca-certificates/ca-certificates_20180409.bb:do_package_qa_setscene) | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 296 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe ca-certificates-20180409-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 297 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe ca-certificates-20180409-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 298 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe util-linux-2.32.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 299 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_package_qa_setscene) | |
| NOTE: recipe util-linux-2.32.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 301 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/intltool/intltool_0.51.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 302 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_populate_lic_setscene) | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 303 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe intltool-native-0.51.0-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe python-2.7.15-r1: task do_package_qa_setscene: Started | |
| NOTE: recipe glibc-locale-2.28-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 304 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_package_qa_setscene) | |
| NOTE: recipe python-2.7.15-r1: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 305 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 306 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_package_qa_setscene) | |
| NOTE: recipe intltool-native-0.51.0-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 307 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 308 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_populate_lic_setscene) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 310 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_package_qa_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe update-rc.d-0.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe acl-2.2.52-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 311 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe libcap-2.25-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 312 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/which/which_2.21.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 313 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_package_qa_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe diffutils-3.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe which-2.21-r3: task do_package_qa_setscene: Started | |
| NOTE: recipe flex-2.6.0-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe which-2.21-r3: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 314 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_package_qa_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 315 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 316 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe flex-2.6.0-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 317 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe eudev-3.2.5-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 318 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/cross-localedef-native_2.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe db-1_5.3.28-r1: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe bash-4.4.18-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 319 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe cross-localedef-native-2.28-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe cross-localedef-native-2.28-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 320 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 321 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe db-1_5.3.28-r1: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 322 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gdbm-1.18-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe perl-5.24.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 324 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_populate_lic_setscene) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 325 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 326 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe gdbm-1.18-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 327 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe db-1_5.3.28-r1: task do_populate_lic_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe db-1_5.3.28-r1: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 328 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_populate_lic_setscene) | |
| NOTE: recipe expat-2.2.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 329 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/libxml-parser-perl_2.44.bb:do_populate_lic_setscene) | |
| NOTE: recipe gmp-6.1.2-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 330 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe libxml-parser-perl-native-2.44-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 331 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 332 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe make-4.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libxml-parser-perl-native-2.44-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 333 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_populate_lic_setscene) | |
| NOTE: recipe make-4.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 334 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 335 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ca-certificates/ca-certificates_20180409.bb:do_populate_lic_setscene) | |
| NOTE: recipe tzdata-2018g-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 336 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_package_qa_setscene) | |
| NOTE: recipe ca-certificates-20180409-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 337 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_package_qa_setscene) | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 338 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/which/which_2.21.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bison-3.0.4-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 339 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe sed-4.2.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 340 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_package_qa_setscene) | |
| NOTE: recipe which-2.21-r3: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe which-2.21-r3: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 341 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 342 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bison-3.0.4-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 344 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe sed-4.2.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 345 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_package_qa_setscene) | |
| NOTE: recipe bison-3.0.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 346 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_package_qa_setscene) | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 347 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 348 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4_1.4.18.bb:do_populate_lic_setscene) | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bison-3.0.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 349 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe m4-1.4.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 350 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4_1.4.18.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 351 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_package_qa_setscene) | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe m4-1.4.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 352 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe m4-1.4.18-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe m4-1.4.18-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 353 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 355 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 356 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_package_qa_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 357 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_package_qa_setscene) | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 358 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_package_qa_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bzip2-1.0.6-r5: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 360 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 361 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cwautomacros/cwautomacros_20110201.bb:do_populate_lic_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 362 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe gmp-6.1.2-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 363 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 364 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu-helper-native_1.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe cwautomacros-native-20110201-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_populate_lic_setscene: Started | |
| NOTE: recipe cwautomacros-native-20110201-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 366 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe grep-3.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 367 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe grep-3.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe xz-5.2.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 368 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 372 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe xz-5.2.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 373 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_populate_lic_setscene) | |
| NOTE: recipe cracklib-2.9.5-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 375 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/libpng/libpng_1.6.35.bb:do_populate_lic_setscene) | |
| NOTE: recipe python-2.7.15-r1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe python-2.7.15-r1: task do_populate_lic_setscene: Started | |
| NOTE: recipe python-2.7.15-r1: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 376 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 377 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 378 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libpcre-8.42-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe gawk-4.2.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: Running setscene task 379 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_package_qa_setscene) | |
| NOTE: recipe libpcre-8.42-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 380 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libxslt/libxslt_1.1.32.bb:do_populate_lic_setscene) | |
| NOTE: recipe python-2.7.15-r1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 381 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe gawk-4.2.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_package_qa_setscene: Started | |
| NOTE: Running setscene task 382 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libxslt-native-1.1.32-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 383 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 384 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe python3-3.5.6-r1.0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libxslt-native-1.1.32-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 385 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe bash-completion-2.8-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe bash-completion-2.8-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 386 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe python3-3.5.6-r1.0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 387 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe tzdata-2018g-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 388 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_populate_lic_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 389 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe gdbm-1.18-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe flex-2.6.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe diffutils-3.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 390 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_packagedata_setscene) | |
| NOTE: recipe gdbm-1.18-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 391 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_populate_lic_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe flex-2.6.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 392 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe lzo-2.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 393 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4_1.4.18.bb:do_package_qa_setscene) | |
| NOTE: recipe diffutils-3.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe lzo-2.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 395 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 396 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe m4-1.4.18-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe m4-1.4.18-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 397 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/m4/m4_1.4.18.bb:do_packagedata_setscene) | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe perl-5.24.4-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 398 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_populate_lic_setscene) | |
| NOTE: recipe m4-1.4.18-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe util-linux-2.32.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe m4-1.4.18-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 400 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_package_write_rpm_setscene) | |
| NOTE: Running setscene task 401 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe readline-7.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe readline-7.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 402 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_populate_lic_setscene) | |
| NOTE: recipe util-linux-2.32.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 403 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 404 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 406 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe openssl-1.1.1a-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpam-1.3.0-r5: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 407 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libpam-1.3.0-r5: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 408 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_package_qa_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 409 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_package_qa_setscene) | |
| NOTE: recipe shadow-native-4.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 410 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 411 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe sed-4.2.2-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 412 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_populate_lic_setscene) | |
| NOTE: recipe shadow-native-4.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 416 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_package_qa_setscene) | |
| NOTE: recipe grep-3.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe shared-mime-info-native-1.10-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe grep-3.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 417 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe dbus-1.12.10-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 418 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_populate_lic_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: recipe shared-mime-info-native-1.10-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 419 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_packagedata_setscene) | |
| NOTE: Running setscene task 425 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ca-certificates/ca-certificates_20180409.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 426 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_populate_lic_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe lzo-2.10-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe bzip2-1.0.6-r5: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 427 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_package_qa_setscene) | |
| NOTE: Running setscene task 428 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe dbus-test-1.12.10-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 430 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe lzo-2.10-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 431 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_populate_lic_setscene) | |
| NOTE: recipe procps-3.3.15-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe procps-3.3.15-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe zlib-1.2.11-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe procps-3.3.15-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 432 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_package_qa_setscene) | |
| NOTE: recipe procps-3.3.15-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 433 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_packagedata_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 434 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_populate_lic_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe update-rc.d-0.8-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 435 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_populate_lic_setscene) | |
| NOTE: recipe procps-3.3.15-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 436 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_packagedata_setscene) | |
| NOTE: recipe attr-2.4.47-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe procps-3.3.15-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 438 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_packagedata_setscene) | |
| NOTE: recipe xorgproto-2018.4-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 439 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe tzdata-2018g-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gawk-4.2.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe attr-2.4.47-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 440 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_package_qa_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe tzdata-2018g-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 442 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzcode/tzcode-native_2018g.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe tzcode-native-2018g-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gawk-4.2.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 444 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_populate_lic_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe util-linux-2.32.1-r0: task do_package_qa_setscene: Started | |
| NOTE: Running setscene task 445 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ca-certificates/ca-certificates_20180409.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe tzcode-native-2018g-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 446 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_package_qa_setscene) | |
| NOTE: recipe util-linux-2.32.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 447 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/btrfs-tools/btrfs-tools_4.17.1.bb:do_packagedata_setscene) | |
| NOTE: recipe unzip-1_6.0-r5: task do_populate_lic_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe glibc-locale-2.28-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe unzip-1_6.0-r5: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 448 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_packagedata_setscene) | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 449 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/debianutils/debianutils_4.8.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 450 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ca-certificates/ca-certificates_20180409.bb:do_packagedata_setscene) | |
| NOTE: recipe bash-4.4.18-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe btrfs-tools-4.17.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 452 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe ca-certificates-20180409-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe debianutils-native-4.8.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe ca-certificates-20180409-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 453 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_packagedata_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bash-4.4.18-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 455 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe debianutils-native-4.8.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 456 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_packagedata_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 457 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_packagedata_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe eudev-3.2.5-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe lzo-2.10-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 460 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe eudev-3.2.5-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 462 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libxslt/libxslt_1.1.32.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glibc-locale-2.28-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 463 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe lzo-2.10-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 465 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_packagedata_setscene) | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxslt-native-1.1.32-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe e2fsprogs-1.44.3-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 466 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_packagedata_setscene) | |
| NOTE: recipe libxslt-native-1.1.32-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 467 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 469 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_package_qa_setscene) | |
| NOTE: recipe grep-3.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 470 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_populate_lic_setscene) | |
| NOTE: recipe lzo-2.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_package_qa_setscene: Started | |
| NOTE: recipe grep-3.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe libpcre-8.42-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 472 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_populate_lic_setscene) | |
| NOTE: Running setscene task 473 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_packagedata_setscene) | |
| NOTE: recipe lzo-2.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 474 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_packagedata_setscene: Started | |
| NOTE: recipe libpcre-8.42-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 475 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/which/which_2.21.bb:do_packagedata_setscene) | |
| NOTE: recipe gnome-desktop-testing-2014.1-r1: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 477 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 479 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe python-2.7.15-r1: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe procps-3.3.15-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bison-3.0.4-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe which-2.21-r3: task do_packagedata_setscene: Started | |
| NOTE: recipe procps-3.3.15-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 480 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_package_qa_setscene) | |
| NOTE: recipe which-2.21-r3: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 482 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cwautomacros/cwautomacros_20110201.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe python-2.7.15-r1: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 483 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_packagedata_setscene) | |
| NOTE: recipe cwautomacros-native-20110201-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxml2-2.9.8-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 484 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe bison-3.0.4-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: recipe cwautomacros-native-20110201-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 485 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_packagedata_setscene) | |
| NOTE: Running setscene task 486 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe python-2.7.15-r1: task do_packagedata_setscene: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe bison-3.0.4-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe xz-5.2.4-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe python-2.7.15-r1: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 488 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_package_qa_setscene) | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 489 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_populate_lic_setscene) | |
| NOTE: recipe xz-5.2.4-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 490 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpam-1.3.0-r5: task do_package_qa_setscene: Started | |
| NOTE: recipe libxml2-2.9.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libpam-1.3.0-r5: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 491 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_packagedata_setscene) | |
| NOTE: recipe opkg-utils-native-0.3.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bison-3.0.4-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 493 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_package_qa_setscene) | |
| NOTE: recipe opkg-utils-native-0.3.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 497 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_package_qa_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 498 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_populate_lic_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 499 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_package_qa_setscene) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: Running setscene task 500 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe coreutils-8.30-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 502 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_packagedata_setscene) | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 503 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe perl-5.24.4-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe update-rc.d-0.8-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 504 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_packagedata_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 505 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_packagedata_setscene) | |
| NOTE: recipe acl-2.2.52-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 506 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_packagedata_setscene) | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe acl-2.2.52-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 507 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gmp-6.1.2-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shared-mime-info-1.10-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 509 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gmp-6.1.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 510 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe perl-5.24.4-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gmp-6.1.2-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 511 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_packagedata_setscene) | |
| NOTE: recipe shared-mime-info-native-1.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libcap-2.25-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe perl-5.24.4-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 513 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_packagedata_setscene) | |
| NOTE: recipe libcap-2.25-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 515 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe shared-mime-info-native-1.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 516 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/intltool/intltool_0.51.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libcap-2.25-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 517 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_packagedata_setscene) | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libxml2-2.9.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe intltool-native-0.51.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 520 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_packagedata_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 521 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_packagedata_setscene) | |
| NOTE: recipe sed-4.2.2-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe intltool-native-0.51.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 523 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 524 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/libxml-parser-perl_2.44.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpcre-8.42-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe db-1_5.3.28-r1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-linux-2.32.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libxml-parser-perl-native-2.44-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe db-1_5.3.28-r1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 525 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_packagedata_setscene) | |
| NOTE: recipe util-linux-2.32.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 527 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_packagedata_setscene) | |
| NOTE: recipe libpcre-8.42-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 529 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_packagedata_setscene) | |
| NOTE: recipe db-1_5.3.28-r1: task do_packagedata_setscene: Started | |
| NOTE: recipe libxml-parser-perl-native-2.44-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 530 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl-native_5.24.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe perl-native-5.24.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe db-1_5.3.28-r1: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 534 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_package_qa_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 536 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe unzip-1_6.0-r5: task do_package_qa_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 538 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_packagedata_setscene) | |
| NOTE: recipe unzip-1_6.0-r5: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 539 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_packagedata_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_packagedata_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 541 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_packagedata_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 542 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_packagedata_setscene) | |
| NOTE: recipe perl-native-5.24.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 543 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_packagedata_setscene) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe make-4.2.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 545 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_packagedata_setscene) | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 546 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_packagedata_setscene) | |
| NOTE: recipe make-4.2.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 548 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_packagedata_setscene) | |
| NOTE: recipe libpam-1.3.0-r5: task do_packagedata_setscene: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 550 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_packagedata_setscene) | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe glibc-locale-2.28-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_packagedata_setscene: Started | |
| NOTE: recipe libpam-1.3.0-r5: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 551 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_packagedata_setscene) | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 553 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/unzip/unzip_6.0.bb:do_packagedata_setscene) | |
| NOTE: recipe unzip-1_6.0-r5: task do_packagedata_setscene: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe expat-2.2.6-r0: task do_packagedata_setscene: Started | |
| NOTE: Running setscene task 554 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_packagedata_setscene) | |
| NOTE: recipe libxml2-2.9.8-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe glibc-locale-2.28-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe unzip-1_6.0-r5: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 556 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_packagedata_setscene) | |
| NOTE: Running setscene task 557 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_packagedata_setscene) | |
| NOTE: recipe expat-2.2.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 560 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_packagedata_setscene) | |
| NOTE: recipe flex-2.6.0-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libxml2-2.9.8-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 563 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe cracklib-2.9.5-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 564 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_packagedata_setscene) | |
| NOTE: recipe cracklib-2.9.5-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 567 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_packagedata_setscene) | |
| NOTE: recipe flex-2.6.0-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 570 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/cross-localedef-native_2.28.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_packagedata_setscene: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 573 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_packagedata_setscene) | |
| NOTE: recipe cross-localedef-native-2.28-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe update-rc.d-0.8-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 575 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_packagedata_setscene) | |
| NOTE: recipe cross-localedef-native-2.28-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 576 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_packagedata_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 577 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_packagedata_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gdbm-1.18-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe zlib-1.2.11-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 580 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_packagedata_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 582 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_packagedata_setscene) | |
| NOTE: recipe xz-5.2.4-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gdbm-1.18-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 584 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_packagedata_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe xz-5.2.4-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 585 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_packagedata_setscene) | |
| NOTE: recipe readline-7.0-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe python3-3.5.6-r1.0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 586 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 587 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu-helper-native_1.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe readline-7.0-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 589 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 591 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_packagedata_setscene) | |
| NOTE: recipe openssl-1.1.1a-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe gdbm-1.18-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 592 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu_3.0.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe gdbm-1.18-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 594 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_packagedata_setscene) | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 597 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_packagedata_setscene: Started | |
| NOTE: recipe readline-7.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe openssl-1.1.1a-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 598 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe readline-7.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 600 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 602 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_packagedata_setscene) | |
| NOTE: recipe xz-5.2.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xz-5.2.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 605 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_package_qa_setscene) | |
| NOTE: recipe attr-2.4.47-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_package_qa_setscene: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_package_qa_setscene: Succeeded | |
| NOTE: Running setscene task 606 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_packagedata_setscene) | |
| NOTE: recipe attr-2.4.47-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 608 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_packagedata_setscene) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 609 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_populate_lic_setscene) | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 611 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_package_write_rpm_setscene) | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_populate_lic_setscene: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_package_write_rpm_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 613 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_populate_lic_setscene: Succeeded | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_package_write_rpm_setscene: Succeeded | |
| NOTE: Running setscene task 614 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_packagedata_setscene) | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 615 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 616 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 618 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_packagedata_setscene) | |
| NOTE: recipe libffi-3.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libpcre-8.42-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 619 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_packagedata_setscene) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 621 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxcb-1.13-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libpcre-8.42-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 622 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxcb-1.13-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 624 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_packagedata_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-linux-2.32.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe util-linux-2.32.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 625 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_packagedata_setscene) | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 627 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_packagedata_setscene) | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 628 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/pixman_0.34.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bzip2-1.0.6-r5: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 629 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 630 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/alsa/alsa-lib_1.1.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 632 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 633 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/libpng/libpng_1.6.35.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe bash-completion-2.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 634 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe bash-completion-2.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 635 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe dbus-1.12.10-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 636 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_packagedata_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 638 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_packagedata_setscene) | |
| NOTE: recipe dbus-1.12.10-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 639 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe xcb-proto-1.13-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 640 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe xorgproto-2018.4-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 641 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe initscripts-1.0-r155: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 643 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 644 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe shadow-4.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 645 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe shadow-4.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 646 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 647 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe attr-2.4.47-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 648 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 649 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe autoconf-archive-2018.03.13-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 651 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe attr-2.4.47-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 652 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libxcb-1.13-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 653 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libpam-1.3.0-r5: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libxcb-1.13-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 655 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 656 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 657 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpam-1.3.0-r5: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 658 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 659 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/flex/flex_2.6.0.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 660 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 661 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_populate_sysroot_setscene) | |
| NOTE: Running setscene task 662 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe flex-2.6.0-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 663 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libice-1_1.0.9-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 664 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe flex-2.6.0-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 665 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe zlib-1.2.11-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe zlib-1.2.11-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 666 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: Running setscene task 667 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 668 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 669 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_packagedata_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 670 of 676 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext_0.19.8.1.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 671 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe xorgproto-2018.4-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: Running setscene task 673 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_packagedata_setscene) | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe xorgproto-2018.4-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 674 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_packagedata_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_packagedata_setscene: Succeeded | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Running setscene task 676 of 676 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_populate_sysroot_setscene) | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_populate_sysroot_setscene: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_populate_sysroot_setscene: Succeeded | |
| NOTE: Executing RunQueue Tasks | |
| NOTE: Running task 337 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/libtool/libtool-cross_2.4.6.bb:do_rm_work) | |
| NOTE: Running task 359 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/gettext/gettext_0.19.8.1.bb:do_rm_work) | |
| NOTE: Running task 634 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxcrypt/libxcrypt_4.1.1.bb:do_rm_work) | |
| NOTE: Running task 648 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_rm_work) | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_rm_work: Started | |
| NOTE: recipe libtool-cross-2.4.6-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 712 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_rm_work) | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_rm_work: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_rm_work: Started | |
| NOTE: recipe util-macros-1_1.19.2-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 726 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/cracklib/cracklib_2.9.5.bb:do_rm_work) | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_rm_work: Started | |
| NOTE: recipe libxcrypt-4.1.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 736 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_rm_work) | |
| NOTE: recipe gettext-native-0.19.8.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 800 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_rm_work) | |
| NOTE: recipe cracklib-2.9.5-r0: task do_rm_work: Started | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_rm_work: Started | |
| NOTE: recipe cracklib-native-2.9.5-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 820 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-util/util-macros_1.19.2.bb:do_rm_work) | |
| NOTE: recipe xorgproto-2018.4-r0: task do_rm_work: Started | |
| NOTE: recipe cracklib-2.9.5-r0: task do_rm_work: Succeeded | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_rm_work: Started | |
| NOTE: Running task 840 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_rm_work) | |
| NOTE: recipe libxml2-native-2.9.8-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 850 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_rm_work) | |
| NOTE: recipe xorgproto-2018.4-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 864 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/xtrans_1.3.5.bb:do_rm_work) | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_rm_work: Started | |
| NOTE: recipe util-macros-native-1_1.19.2-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 884 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/libpng/libpng_1.6.35.bb:do_rm_work) | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_rm_work: Started | |
| NOTE: recipe libffi-native-3.2.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 894 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/pixman_0.34.0.bb:do_rm_work) | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_rm_work: Started | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_rm_work: Started | |
| NOTE: recipe glib-2.0-native-1_2.58.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 904 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-multimedia/alsa/alsa-lib_1.1.6.bb:do_rm_work) | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_rm_work: Started | |
| NOTE: recipe xtrans-1_1.3.5-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 914 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu_3.0.0.bb:do_rm_work) | |
| NOTE: recipe libpng-native-1.6.35-r0: task do_rm_work: Succeeded | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_rm_work: Started | |
| NOTE: Running task 928 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libffi/libffi_3.2.1.bb:do_rm_work) | |
| NOTE: recipe pixman-native-1_0.34.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 942 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-passwd/base-passwd_3.5.29.bb:do_rm_work) | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_rm_work: Started | |
| NOTE: recipe alsa-lib-native-1.1.6-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 966 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/readline/readline_7.0.bb:do_rm_work) | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_rm_work: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_rm_work: Started | |
| NOTE: recipe qemu-native-3.0.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 987 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/sqlite/sqlite3_3.23.1.bb:do_rm_work) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_rm_work: Started | |
| NOTE: recipe libffi-3.2.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1009 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu-helper-native_1.0.bb:do_addto_recipe_sysroot) | |
| NOTE: recipe base-passwd-3.5.29-r0: task do_rm_work: Succeeded | |
| NOTE: recipe readline-7.0-r0: task do_rm_work: Started | |
| NOTE: Running task 1025 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_rm_work) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_rm_work: Started | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_addto_recipe_sysroot: Started | |
| NOTE: recipe readline-7.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1040 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxdmcp_1.1.2.bb:do_rm_work) | |
| NOTE: recipe sqlite3-3_3.23.1-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1054 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxau_1.0.8.bb:do_rm_work) | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_rm_work: Started | |
| NOTE: recipe opkg-utils-0.3.6-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1068 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libpthread-stubs_0.4.bb:do_rm_work) | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_rm_work: Started | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_addto_recipe_sysroot: Succeeded | |
| NOTE: Running task 1069 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/qemu/qemu-helper-native_1.0.bb:do_rm_work) | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_rm_work: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_rm_work: Started | |
| NOTE: recipe libxdmcp-1_1.1.2-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1083 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xcb-proto_1.13.bb:do_rm_work) | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_rm_work: Started | |
| NOTE: recipe libxau-1_1.0.8-r0: task do_rm_work: Succeeded | |
| NOTE: recipe libpthread-stubs-0.4-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1097 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libice_1.0.9.bb:do_rm_work) | |
| NOTE: Running task 1111 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libxcb_1.13.bb:do_rm_work) | |
| NOTE: recipe qemu-helper-native-1.0-r1: task do_rm_work: Succeeded | |
| NOTE: Running task 1121 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-proto/xorgproto_2018.4.bb:do_rm_work) | |
| NOTE: recipe xcb-proto-1.13-r0: task do_rm_work: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_rm_work: Started | |
| NOTE: recipe xcb-proto-1.13-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1135 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libsm_1.2.2.bb:do_rm_work) | |
| NOTE: recipe libxcb-1.13-r0: task do_rm_work: Started | |
| NOTE: recipe libice-1_1.0.9-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1149 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-graphics/xorg-lib/libx11_1.6.6.bb:do_rm_work) | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_rm_work: Started | |
| NOTE: recipe libxcb-1.13-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1159 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_rm_work) | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_rm_work: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_rm_work: Started | |
| NOTE: recipe xorgproto-native-2018.4-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1173 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/update-rc.d/update-rc.d_0.8.bb:do_rm_work) | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_rm_work: Started | |
| NOTE: recipe libx11-1_1.6.6-r0: task do_rm_work: Succeeded | |
| NOTE: recipe libsm-1_1.2.2-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1187 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/initscripts/initscripts_1.0.bb:do_rm_work) | |
| NOTE: Running task 1199 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_fetch) | |
| NOTE: recipe update-rc.d-0.8-r0: task do_rm_work: Started | |
| NOTE: recipe update-rc.d-native-0.8-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1213 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-sysroot_4.6.bb:do_rm_work) | |
| NOTE: recipe base-files-3.0.14-r89: task do_fetch: Started | |
| NOTE: recipe initscripts-1.0-r155: task do_rm_work: Started | |
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| NOTE: Running task 1227 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/expat/expat_2.2.6.bb:do_rm_work) | |
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| NOTE: Running task 1228 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_prepare_recipe_sysroot) | |
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| NOTE: Running task 1229 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_unpack) | |
| NOTE: recipe base-files-3.0.14-r89: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe expat-2.2.6-r0: task do_rm_work: Started | |
| NOTE: recipe shadow-sysroot-4.6-r3: task do_rm_work: Succeeded | |
| NOTE: recipe base-files-3.0.14-r89: task do_prepare_recipe_sysroot: Succeeded | |
| NOTE: Running task 1243 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/autoconf-archive/autoconf-archive_2018.03.13.bb:do_rm_work) | |
| NOTE: Running task 1253 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow_4.6.bb:do_rm_work) | |
| NOTE: recipe base-files-3.0.14-r89: task do_unpack: Started | |
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| NOTE: Running task 1339 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/db/db_5.3.28.bb:do_rm_work) | |
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| NOTE: recipe shadow-native-4.6-r0: task do_rm_work: Started | |
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| NOTE: Running task 1349 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/cross-localedef-native_2.28.bb:do_rm_work) | |
| NOTE: recipe db-1_5.3.28-r1: task do_rm_work: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_unpack: Succeeded | |
| NOTE: Running task 1359 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glibc/glibc-locale_2.28.bb:do_rm_work) | |
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| NOTE: Running task 1360 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_patch) | |
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| NOTE: Running task 1418 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/bash-completion/bash-completion_2.8.bb:do_rm_work) | |
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| NOTE: recipe glibc-locale-2.28-r0: task do_rm_work: Started | |
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| NOTE: Running task 1419 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_populate_lic) | |
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| NOTE: Running task 1421 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_configure) | |
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| NOTE: recipe base-files-3.0.14-r89: task do_configure: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_populate_lic: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_configure: Succeeded | |
| NOTE: Running task 1422 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_compile) | |
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| NOTE: Running task 1432 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl-native_5.24.4.bb:do_rm_work) | |
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| NOTE: Running task 1556 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/lzo/lzo_2.10.bb:do_rm_work) | |
| NOTE: recipe base-files-3.0.14-r89: task do_compile: Started | |
| NOTE: recipe perl-native-5.24.4-r0: task do_rm_work: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_compile: Succeeded | |
| NOTE: Running task 1558 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/perl_5.24.4.bb:do_rm_work) | |
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| NOTE: Running task 1560 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libpcre/libpcre_8.42.bb:do_rm_work) | |
| NOTE: recipe lzo-2.10-r0: task do_rm_work: Started | |
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| NOTE: Running task 1562 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-connectivity/openssl/openssl_1.1.1a.bb:do_rm_work) | |
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| NOTE: recipe perl-5.24.4-r0: task do_rm_work: Started | |
| NOTE: recipe lzo-2.10-r0: task do_rm_work: Succeeded | |
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| NOTE: Running task 1564 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gdbm/gdbm_1.18.bb:do_rm_work) | |
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| NOTE: Running task 1567 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/ptest-runner/ptest-runner_2.2.bb:do_rm_work) | |
| NOTE: recipe perl-5.24.4-r0: task do_rm_work: Succeeded | |
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| NOTE: Running task 1568 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_install) | |
| NOTE: recipe gdbm-1.18-r0: task do_rm_work: Started | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_rm_work: Started | |
| NOTE: Running task 1624 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gmp/gmp_6.1.2.bb:do_rm_work) | |
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| NOTE: Running task 1638 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libcap/libcap_2.25.bb:do_rm_work) | |
| NOTE: recipe ptest-runner-2.2+gitAUTOINC+49956f65bb-r0: task do_rm_work: Succeeded | |
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| NOTE: Running task 1686 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/opkg-utils/opkg-utils_0.3.6.bb:do_rm_work) | |
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| NOTE: Running task 1688 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/xz/xz_5.2.4.bb:do_rm_work) | |
| NOTE: recipe libcap-2.25-r0: task do_rm_work: Started | |
| NOTE: recipe opkg-utils-native-0.3.6-r0: task do_rm_work: Started | |
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| NOTE: Running task 1690 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bzip2/bzip2_1.0.6.bb:do_rm_work) | |
| NOTE: recipe xz-5.2.4-r0: task do_rm_work: Started | |
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| NOTE: Running task 1692 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/kmod/kmod_git.bb:do_rm_work) | |
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| NOTE: Running task 1694 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/gawk/gawk_4.2.1.bb:do_rm_work) | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_rm_work: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_install: Started | |
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| NOTE: Running task 1696 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/ncurses/ncurses_6.1+20180630.bb:do_rm_work) | |
| NOTE: recipe gawk-4.2.1-r0: task do_rm_work: Started | |
| NOTE: recipe kmod-25+gitAUTOINC+aca4eca103-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1706 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/libxslt/libxslt_1.1.32.bb:do_rm_work) | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_rm_work: Started | |
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| NOTE: Running task 1720 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/perl/libxml-parser-perl_2.44.bb:do_rm_work) | |
| NOTE: recipe libxslt-native-1.1.32-r0: task do_rm_work: Started | |
| NOTE: recipe ncurses-6.1+20180630-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1737 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/libxml/libxml2_2.9.8.bb:do_rm_work) | |
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| NOTE: Running task 1739 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/sed/sed_4.2.2.bb:do_rm_work) | |
| NOTE: recipe base-files-3.0.14-r89: task do_install: Succeeded | |
| NOTE: Running task 1741 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/diffutils/diffutils_3.6.bb:do_rm_work) | |
| NOTE: recipe libxml-parser-perl-native-2.44-r0: task do_rm_work: Started | |
| NOTE: recipe libxml2-2.9.8-r0: task do_rm_work: Started | |
| NOTE: recipe sed-4.2.2-r0: task do_rm_work: Started | |
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| NOTE: Running task 1743 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/zlib/zlib_1.2.11.bb:do_rm_work) | |
| NOTE: recipe diffutils-3.6-r0: task do_rm_work: Started | |
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| NOTE: Running task 1745 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_package) | |
| NOTE: recipe zlib-1.2.11-r0: task do_rm_work: Started | |
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| NOTE: Running task 1746 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_populate_sysroot) | |
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| NOTE: Running task 1748 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/make/make_4.2.1.bb:do_rm_work) | |
| NOTE: recipe base-files-3.0.14-r89: task do_package: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_populate_sysroot: Started | |
| NOTE: recipe make-4.2.1-r0: task do_rm_work: Started | |
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| NOTE: Running task 1758 of 2113 (virtual:native:/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/intltool/intltool_0.51.0.bb:do_rm_work) | |
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| NOTE: Running task 1774 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/pam/libpam_1.3.0.bb:do_rm_work) | |
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| NOTE: Running task 1776 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/acl_2.2.52.bb:do_rm_work) | |
| NOTE: recipe libpam-1.3.0-r5: task do_rm_work: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_populate_sysroot: Succeeded | |
| NOTE: Running task 1779 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/attr/attr_2.4.47.bb:do_rm_work) | |
| NOTE: recipe acl-2.2.52-r0: task do_rm_work: Started | |
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| NOTE: Running task 1781 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/coreutils/coreutils_8.30.bb:do_rm_work) | |
| NOTE: recipe attr-2.4.47-r0: task do_rm_work: Started | |
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| NOTE: Running task 1808 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_fetch) | |
| NOTE: recipe coreutils-8.30-r0: task do_rm_work: Started | |
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| NOTE: Running noexec task 1809 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_fetch) | |
| NOTE: Running task 1810 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_prepare_recipe_sysroot) | |
| NOTE: recipe make-mod-scripts-1.0-r0: task do_fetch: Started | |
| NOTE: recipe make-mod-scripts-1.0-r0: task do_fetch: Succeeded | |
| NOTE: Running task 1811 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_prepare_recipe_sysroot) | |
| NOTE: recipe coreutils-8.30-r0: task do_rm_work: Succeeded | |
| NOTE: Running task 1812 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_unpack) | |
| NOTE: recipe kernel-devsrc-1.0-r0: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe make-mod-scripts-1.0-r0: task do_prepare_recipe_sysroot: Started | |
| NOTE: recipe make-mod-scripts-1.0-r0: task do_unpack: Started | |
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| NOTE: Running task 1813 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_patch) | |
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| NOTE: Running noexec task 1814 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_unpack) | |
| NOTE: Running noexec task 1815 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_patch) | |
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| NOTE: recipe kernel-devsrc-1.0-r0: task do_populate_lic: Started | |
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| NOTE: Running task 1830 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python_2.7.15.bb:do_rm_work) | |
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| NOTE: recipe python-2.7.15-r1: task do_rm_work: Started | |
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| NOTE: Running task 1835 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_configure) | |
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| NOTE: Running task 1850 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_rm_work) | |
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| NOTE: recipe bc-1.07.1-r0: task do_populate_lic: Started | |
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| NOTE: Running task 1875 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bc/bc_1.07.1.bb:do_configure) | |
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| NOTE: Running task 1885 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzcode/tzcode-native_2018g.bb:do_rm_work) | |
| NOTE: recipe bc-1.07.1-r0: task do_configure: Started | |
| NOTE: recipe tzcode-native-2018g-r0: task do_rm_work: Started | |
| NOTE: recipe base-files-3.0.14-r89: task do_package: Succeeded | |
| NOTE: Running task 1886 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_packagedata) | |
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| NOTE: Running task 1900 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/python/python3_3.5.6.bb:do_rm_work) | |
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| NOTE: recipe python3-3.5.6-r1.0: task do_rm_work: Started | |
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| NOTE: Running task 1901 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_package_qa) | |
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| NOTE: Running task 1903 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_package_write_rpm) | |
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| NOTE: Running task 1905 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/bash/bash_4.4.18.bb:do_rm_work) | |
| NOTE: recipe bash-4.4.18-r0: task do_rm_work: Started | |
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| NOTE: Running task 1914 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/udev/eudev_3.2.5.bb:do_rm_work) | |
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| NOTE: Running task 1915 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/base-files/base-files_3.0.14.bb:do_rm_work) | |
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| NOTE: recipe base-files-3.0.14-r89: task do_rm_work: Started | |
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| NOTE: Running task 1921 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus_1.12.10.bb:do_rm_work) | |
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| NOTE: Running task 1923 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/dbus/dbus-test_1.12.10.bb:do_rm_work) | |
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| NOTE: Running task 1925 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_fetch) | |
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| NOTE: recipe shadow-securetty-4.6-r3: task do_fetch: Started | |
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| NOTE: Running task 1926 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_prepare_recipe_sysroot) | |
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| NOTE: Running task 1927 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_unpack) | |
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| NOTE: Running task 1941 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/shared-mime-info/shared-mime-info_1.10.bb:do_rm_work) | |
| NOTE: recipe shadow-securetty-4.6-r3: task do_unpack: Started | |
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| NOTE: Running task 1942 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_patch) | |
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| NOTE: recipe shadow-securetty-4.6-r3: task do_patch: Started | |
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| NOTE: Running task 1943 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_populate_lic) | |
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| NOTE: Running task 1944 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_configure) | |
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| NOTE: recipe shadow-securetty-4.6-r3: task do_configure: Started | |
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| NOTE: Running task 1945 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_compile) | |
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| NOTE: Running task 1960 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-devtools/e2fsprogs/e2fsprogs_1.44.3.bb:do_rm_work) | |
| NOTE: recipe shadow-securetty-4.6-r3: task do_compile: Started | |
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| NOTE: Running task 1962 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/procps/procps_3.3.15.bb:do_rm_work) | |
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| NOTE: Running task 1963 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_install) | |
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| NOTE: Running task 1977 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/tzdata/tzdata_2018g.bb:do_rm_work) | |
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| NOTE: recipe shadow-securetty-4.6-r3: task do_install: Started | |
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| NOTE: Running task 1991 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/glib-2.0/glib-2.0_2.58.0.bb:do_rm_work) | |
| NOTE: recipe shadow-securetty-4.6-r3: task do_install: Succeeded | |
| NOTE: Running task 1993 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_package) | |
| NOTE: recipe shadow-securetty-4.6-r3: task do_package: Started | |
| NOTE: recipe glib-2.0-1_2.58.0-r0: task do_rm_work: Started | |
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| NOTE: Running task 1995 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-support/gnome-desktop-testing/gnome-desktop-testing_2014.1.bb:do_rm_work) | |
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| NOTE: Running task 2010 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/grep/grep_3.1.bb:do_rm_work) | |
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| NOTE: Running task 2011 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_packagedata) | |
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| NOTE: recipe bc-1.07.1-r0: task do_configure: Succeeded | |
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| NOTE: recipe m4-1.4.18-r0: task do_rm_work: Started | |
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| NOTE: Running task 2035 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-extended/shadow/shadow-securetty_4.6.bb:do_rm_work) | |
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| NOTE: Running task 2063 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-core/util-linux/util-linux_2.32.1.bb:do_rm_work) | |
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| NOTE: Running task 2090 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/make-mod-scripts/make-mod-scripts_1.0.bb:do_compile) | |
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| NOTE: recipe make-mod-scripts-1.0-r0: task do_install: Started | |
| NOTE: recipe kernel-devsrc-1.0-r0: task do_install: Started | |
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| NOTE: recipe kernel-devsrc-1.0-r0: task do_package_write_rpm: Succeeded | |
| NOTE: Running task 2111 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_rm_work) | |
| NOTE: recipe kernel-devsrc-1.0-r0: task do_rm_work: Started | |
| NOTE: recipe kernel-devsrc-1.0-r0: task do_rm_work: Succeeded | |
| NOTE: Running noexec task 2112 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_rm_work_all) | |
| NOTE: Running noexec task 2113 of 2113 (/opt/pkg/petalinux/2019.1/components/yocto/source/arm/layers/core/meta/recipes-kernel/linux/kernel-devsrc.bb:do_build) | |
| NOTE: Tasks Summary: Attempted 2113 tasks of which 1946 didn't need to be rerun and all succeeded. | |
| INFO: Copying Images from deploy to images | |
| NOTE: Failed to copy built images to tftp dir: /tftpboot | |
| [INFO] successfully built kernel-devsrc | |
| cp -f /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/build/tmp/deploy/rpm/*/kernel-devsrc-1.0-r0.*.rpm /home/pcarr/PYNQ/sdbuild/build/Pynq-Z1/petalinux_project/build/tmp/deploy/rpm/kernel-devsrc-1.0-r0.plnx_arm.rpm | |
| cp --sparse=always /home/pcarr/Downloads/bionic.arm.2.5.img /home/pcarr/PYNQ/sdbuild/output/Pynq-Z1-2.5.img | |
| /home/pcarr/PYNQ/sdbuild/scripts/mount_image.sh /home/pcarr/PYNQ/sdbuild/output/Pynq-Z1-2.5.img /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1 | |
| loop0p1 | |
| loop0p2 | |
| QEMU_EXE=/opt/qemu/bin/qemu-arm-static PYNQ_BOARDDIR=/home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1 PYNQ_BOARD=Pynq-Z1 ARCH=arm PACKAGE_PATH=/home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/packages /home/pcarr/PYNQ/sdbuild/scripts/install_packages.sh /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1 pynq boot_leds ethernet | |
| + target=/home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1 | |
| + shift | |
| + fss='proc run dev' | |
| + for fs in '$fss' | |
| + sudo mount -o bind /proc /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1/proc | |
| + for fs in '$fss' | |
| + sudo mount -o bind /run /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1/run | |
| + for fs in '$fss' | |
| + sudo mount -o bind /dev /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1/dev | |
| + mkdir -p /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1/ccache | |
| + sudo mount -o bind /home/pcarr/PYNQ/sdbuild/ccache /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1/ccache | |
| + trap unmount_special EXIT | |
| + export CFLAGS= | |
| + CFLAGS= | |
| + export CPPFLAGS= | |
| + CPPFLAGS= | |
| + export PATH=/usr/lib/ccache:/opt/pkg/petalinux/2019.1/tools/xsct/petalinux/bin:/opt/pkg/petalinux/2019.1/tools/common/petalinux/bin:/opt/pkg/petalinux/2019.1/tools/xsct/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/microblaze/lin/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/bin:/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/opt/Xilinx/DocNav:/opt/Xilinx/Vivado/2019.1/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/home/pcarr/bin:/home/pcarr/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin | |
| + PATH=/usr/lib/ccache:/opt/pkg/petalinux/2019.1/tools/xsct/petalinux/bin:/opt/pkg/petalinux/2019.1/tools/common/petalinux/bin:/opt/pkg/petalinux/2019.1/tools/xsct/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/microblaze/lin/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/opt/pkg/petalinux/2019.1/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/bin:/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/opt/Xilinx/DocNav:/opt/Xilinx/Vivado/2019.1/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/home/pcarr/bin:/home/pcarr/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin | |
| + export CCACHE_DIR=/ccache | |
| + CCACHE_DIR=/ccache | |
| + export CCACHE_MAXSIZE=15G | |
| + CCACHE_MAXSIZE=15G | |
| + export CCACHE_SLOPPINESS=file_macro,time_macros | |
| + CCACHE_SLOPPINESS=file_macro,time_macros | |
| + export CC=/usr/lib/ccache/gcc | |
| + CC=/usr/lib/ccache/gcc | |
| + export CXX=/usr/lib/ccache/g++ | |
| + CXX=/usr/lib/ccache/g++ | |
| + for p in '$@' | |
| + '[' -n /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/packages -a -e /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/packages/pynq ']' | |
| + f=/home/pcarr/PYNQ/sdbuild/packages/pynq | |
| + '[' -e /home/pcarr/PYNQ/sdbuild/packages/pynq/pre.sh ']' | |
| + /home/pcarr/PYNQ/sdbuild/packages/pynq/pre.sh /home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1 | |
| + set -e | |
| + target=/home/pcarr/PYNQ/sdbuild/build/bionic.Pynq-Z1 | |
| +++ dirname /home/pcarr/PYNQ/sdbuild/packages/pynq/pre.sh | |
| ++ cd /home/pcarr/PYNQ/sdbuild/packages/pynq | |
| ++ pwd | |
| + script_dir=/home/pcarr/PYNQ/sdbuild/packages/pynq | |
| + '[' Pynq-Z1 '!=' Unknown ']' | |
| + cd /home/pcarr/PYNQ/sdbuild/../boards/Pynq-Z1/.. | |
| + '[' -d .git ']' | |
| + '[' '!' -d /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z1 ']' | |
| + cd /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards | |
| + '[' Pynq-Z1 == Unknown ']' | |
| + boards=Pynq-Z1 | |
| + cd /home/pcarr/PYNQ/sdbuild/build/PYNQ | |
| + ./build.sh | |
| ./build.sh | |
| Script for building default overlays, microblaze bsp's and binaries. | |
| building bitstream base.bit for ZCU104 | |
| make[1]: Entering directory '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base' | |
| vivado -mode batch -source build_base_ip.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source build_base_ip.tcl -notrace | |
| Building color_convert_2 IP | |
| Checking color_convert_2 | |
| Building pixel_pack_2 IP | |
| Checking pixel_pack_2 | |
| Building pixel_unpack_2 IP | |
| Checking pixel_unpack_2 | |
| HLS IP builds complete | |
| INFO: [Common 17-206] Exiting Vivado at Fri Nov 1 16:47:56 2019... | |
| vivado -mode batch -source base.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source base.tcl -notrace | |
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |
| INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ip'. | |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.1/data/ip'. | |
| INFO: [BD_TCL-3] Currently there is no design <base> in project, so creating one... | |
| Wrote : </home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/base.bd> | |
| INFO: [BD_TCL-4] Making design <base> as current_bd_design. | |
| INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "base". | |
| INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: | |
| xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_register_slice:2.1 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:ip:pr_axi_shutdown_manager:1.0 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:xlconcat:2.1 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:hls:color_convert_2:1.0 xilinx.com:ip:v_hdmi_rx_ss:3.1 xilinx.com:hls:pixel_pack_2:1.0 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:axis_register_slice:1.1 xilinx.com:ip:v_hdmi_tx_ss:3.1 xilinx.com:hls:pixel_unpack_2:1.0 xilinx.com:ip:vid_phy_controller:2.2 . | |
| INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide. | |
| INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide. | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_tri_o is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod0/clk_100M(clk) and /iop_pmod0/dff_en_reset_vector_0/clk(undef) | |
| INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_1: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide. | |
| INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_1: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide. | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_tri_o is being overridden by the user. This pin will not be connected as a part of interface connection io | |
| WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod1/clk_100M(clk) and /iop_pmod1/dff_en_reset_vector_0/clk(undef) | |
| INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose. | |
| INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change | |
| INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e | |
| create_bd_cell: Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 2905.133 ; gain = 1001.824 ; free physical = 338 ; free virtual = 13863 | |
| WARNING: [BD 41-1306] The connection to interface pin /reset_control/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_0/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_1/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_2/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /proc_sys_reset_3/dcm_locked(undef) and /ps_e_0/pl_resetn0(rst) | |
| WARNING: [BD 41-1306] The connection to interface pin /ps_e_0/emio_gpio_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0 | |
| Excluding </ps_e_0/SAXIGP4/HP2_DDR_LOW> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_LPS_OCM> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_LPS_OCM> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_QSPI> from </video/axi_vdma/Data_MM2S> | |
| WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter C_M_AXI_S2MM_DATA_WIDTH(128) on '/video/axi_vdma' with propagated value(64). Command ignored | |
| INFO: [PSU-1] DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change | |
| WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc_0: Property SENSITIVITY = "NULL" for interrupt input 6 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary. | |
| WARNING: [xilinx.com:ip:axi_intc:4.1-6] /axi_intc_0: Property SENSITIVITY = "NULL" for interrupt input 5 not recognized - using default interrupt type Rising Edge. Please change this manually if necessary. | |
| INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /iop_pmod1/spi | |
| ####################################################################################### | |
| INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. | |
| ######################################################################################## | |
| INFO: [xilinx.com:ip:axi_quad_spi:3.2-1] /iop_pmod0/spi | |
| ####################################################################################### | |
| INFO: AXI Quad SPI core's AXI Lite Clock and EXT SPI CLK are synchronous to each other. | |
| ######################################################################################## | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e_0/S_AXI_HP0_FPD(1) and /shutdown_HP0_FPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e_0/S_AXI_HP0_FPD(1) and /shutdown_HP0_FPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e_0/S_AXI_HP2_FPD(1) and /shutdown_HP2_FPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e_0/S_AXI_HP2_FPD(1) and /shutdown_HP2_FPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps_e_0/S_AXI_LPD(1) and /shutdown_LPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps_e_0/S_AXI_LPD(1) and /shutdown_LPD/M_AXI(0) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/i00_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M00_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/i00_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M00_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/i02_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M02_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/i02_couplers/auto_ds/S_AXI(0) and /axi_interconnect/xbar/M02_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m11_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M03_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m11_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M03_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m12_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M04_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m12_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M04_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m13_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M05_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m13_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M05_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m14_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M06_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m14_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M06_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m15_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M07_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m15_couplers/auto_ds/S_AXI(0) and /axi_interconnect/tier2_xbar_1/M07_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m08_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m08_couplers/auto_cc/M_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m08_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m08_couplers/auto_cc/M_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m09_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m09_couplers/auto_cc/M_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m09_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m09_couplers/auto_cc/M_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /axi_interconnect/m10_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m10_couplers/auto_cc/M_AXI(16) | |
| WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /axi_interconnect/m10_couplers/auto_ds/S_AXI(0) and /axi_interconnect/m10_couplers/auto_cc/M_AXI(16) | |
| validate_bd_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2905.133 ; gain = 0.000 ; free physical = 275 ; free virtual = 13802 | |
| Wrote : </home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/base.bd> | |
| INFO: [Common 17-206] Exiting Vivado at Fri Nov 1 16:49:27 2019... | |
| vivado -mode batch -source build_bitstream.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source build_bitstream.tcl -notrace | |
| Scanning sources... | |
| Finished scanning sources | |
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |
| INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ip'. | |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.1/data/ip'. | |
| open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1455.004 ; gain = 59.234 ; free physical = 1462 ; free virtual = 15045 | |
| Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - axi_intc_0 | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_0 | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_1 | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - tier2_xbar_2 | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_ds | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_clock_converter:2.1 - auto_cc | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_interconnect_0 | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us | |
| Adding component instance block -- xilinx.com:ip:axi_protocol_converter:2.1 - auto_pc | |
| Adding component instance block -- xilinx.com:ip:axi_dwidth_converter:2.1 - auto_us | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_mem_intercon | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - axi_mem_intercon_1 | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - axi_register_slice_0 | |
| Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - fmch_axi_iic | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_btns | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_leds | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio_sws | |
| Adding component instance block -- xilinx.com:user:dff_en_reset_vector:1.0 - dff_en_reset_vector_0 | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio | |
| Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - iic | |
| Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - intc | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - intr | |
| Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - intr_concat | |
| Adding component instance block -- xilinx.com:user:io_switch:1.1 - io_switch | |
| Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10 | |
| Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10 | |
| Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram | |
| Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - lmb_bram_if_cntlr | |
| Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - logic_1 | |
| Adding component instance block -- xilinx.com:ip:microblaze:11.0 - mb | |
| Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - mb_bram_ctrl | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - microblaze_0_axi_periph | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m01_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m02_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m03_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m04_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m05_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m06_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m07_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_mmu:2.1 - s00_mmu | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M | |
| Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - spi | |
| Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - timer | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod0/clk_100M(clk) and /iop_pmod0/dff_en_reset_vector_0/clk(undef) | |
| Adding component instance block -- xilinx.com:user:dff_en_reset_vector:1.0 - dff_en_reset_vector_0 | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - gpio | |
| Adding component instance block -- xilinx.com:ip:axi_iic:2.0 - iic | |
| Adding component instance block -- xilinx.com:ip:axi_intc:4.1 - intc | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - intr | |
| Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - intr_concat | |
| Adding component instance block -- xilinx.com:user:io_switch:1.1 - io_switch | |
| Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - dlmb_v10 | |
| Adding component instance block -- xilinx.com:ip:lmb_v10:3.0 - ilmb_v10 | |
| Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - lmb_bram | |
| Adding component instance block -- xilinx.com:ip:lmb_bram_if_cntlr:4.0 - lmb_bram_if_cntlr | |
| Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - logic_1 | |
| Adding component instance block -- xilinx.com:ip:microblaze:11.0 - mb | |
| Adding component instance block -- xilinx.com:ip:axi_bram_ctrl:4.1 - mb_bram_ctrl | |
| Adding component instance block -- xilinx.com:ip:axi_interconnect:2.1 - microblaze_0_axi_periph | |
| Adding component instance block -- xilinx.com:ip:axi_crossbar:2.1 - xbar | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - s00_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m00_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m01_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m02_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m03_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m04_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m05_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m06_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_register_slice:2.1 - m07_regslice | |
| Adding component instance block -- xilinx.com:ip:axi_mmu:2.1 - s00_mmu | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_clk_wiz_1_100M | |
| Adding component instance block -- xilinx.com:ip:axi_quad_spi:3.2 - spi | |
| Adding component instance block -- xilinx.com:ip:axi_timer:2.0 - timer | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod1/clk_100M(clk) and /iop_pmod1/dff_en_reset_vector_0/clk(undef) | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_intr_ack | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod0_reset | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod1_intr_ack | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - mb_iop_pmod1_reset | |
| Adding component instance block -- xilinx.com:ip:mdm:3.2 - mdm | |
| Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - pmod0_buf | |
| Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - pmod1_buf | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0 | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_1 | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_2 | |
| Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_3 | |
| Adding component instance block -- xilinx.com:ip:zynq_ultra_ps_e:3.3 - ps_e_0 | |
| Adding component instance block -- xilinx.com:ip:axi_gpio:2.0 - reset_control | |
| Adding component instance block -- xilinx.com:ip:pr_axi_shutdown_manager:1.0 - shutdown_HP0_FPD | |
| Adding component instance block -- xilinx.com:ip:pr_axi_shutdown_manager:1.0 - shutdown_HP2_FPD | |
| Adding component instance block -- xilinx.com:ip:pr_axi_shutdown_manager:1.0 - shutdown_LPD | |
| Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - vcc_const | |
| Adding component instance block -- xilinx.com:ip:axi_vdma:6.3 - axi_vdma | |
| Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - const_gnd | |
| Adding component instance block -- xilinx.com:hls:color_convert_2:1.0 - color_convert | |
| Adding component instance block -- xilinx.com:ip:v_hdmi_rx_ss:3.1 - frontend | |
| Adding component instance block -- xilinx.com:hls:pixel_pack_2:1.0 - pixel_pack | |
| Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - pixel_reorder | |
| Adding component instance block -- xilinx.com:ip:axis_register_slice:1.1 - rx_video_axis_reg_slice | |
| Adding component instance block -- xilinx.com:hls:color_convert_2:1.0 - color_convert | |
| Adding component instance block -- xilinx.com:ip:v_hdmi_tx_ss:3.1 - frontend | |
| Adding component instance block -- xilinx.com:ip:axis_subset_converter:1.1 - pixel_reorder | |
| Adding component instance block -- xilinx.com:hls:pixel_unpack_2:1.0 - pixel_unpack | |
| Adding component instance block -- xilinx.com:ip:axis_register_slice:1.1 - tx_video_axis_reg_slice | |
| Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - dru_ibufds_gt_odiv2 | |
| Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - gt_refclk_buf | |
| Adding component instance block -- xilinx.com:ip:xlconstant:1.1 - vcc_const0 | |
| Adding component instance block -- xilinx.com:ip:vid_phy_controller:2.2 - vid_phy_controller | |
| Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat0 | |
| Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0 | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_0 | |
| Adding component instance block -- xilinx.com:ip:xlslice:1.0 - xlslice_1 | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_0/dcm_locked(undef) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_1/dcm_locked(undef) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_2/dcm_locked(undef) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /ps_e_0/pl_resetn0(rst) and /proc_sys_reset_3/dcm_locked(undef) | |
| Excluding </ps_e_0/SAXIGP4/HP2_DDR_LOW> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_LPS_OCM> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_LPS_OCM> from </video/axi_vdma/Data_MM2S> | |
| Excluding </ps_e_0/SAXIGP4/HP2_QSPI> from </video/axi_vdma/Data_MM2S> | |
| Successfully read diagram <base> from BD file <./base/base.srcs/sources_1/bd/base/base.bd> | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /v_hdmi_rx/m_axis_video_aresetn_out(undef) and /v_vid_in_axi4s/aresetn(rst) | |
| WARNING: [BD 41-1731] Type mismatch between connected pins: /v_hdmi_tx/s_axis_video_aresetn_out(undef) and /v_axi4s_vid_out/aresetn(rst) | |
| INFO: [BD 41-1662] The design 'base.bd' is already validated. Therefore parameter propagation will not be re-run. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to net 'shutdown_HP0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to net 'shutdown_HP0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to net 'shutdown_HP0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to net 'shutdown_HP0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to net 'shutdown_HP2_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to net 'shutdown_HP2_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to net 'shutdown_HP2_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to net 'shutdown_HP2_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/synth/base.v | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to net 'shutdown_HP0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to net 'shutdown_HP0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to net 'shutdown_HP0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to net 'shutdown_HP0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to net 'shutdown_HP2_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to net 'shutdown_HP2_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to net 'shutdown_HP2_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to net 'shutdown_HP2_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/sim/base.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hdl/base_wrapper.v | |
| INFO: [BD 41-1662] The design 'base.bd' is already validated. Therefore parameter propagation will not be re-run. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to net 'shutdown_HP0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to net 'shutdown_HP0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to net 'shutdown_HP0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to net 'shutdown_HP0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to net 'shutdown_HP2_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to net 'shutdown_HP2_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to net 'shutdown_HP2_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to net 'shutdown_HP2_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/synth/base.v | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod0/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/iop_pmod1/lmb/lmb_bram/addrb'(32) to net 'Conn1_ADDR'(16) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_awid'(6) to net 'shutdown_HP0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_bid'(1) to net 'shutdown_HP0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp2_arid'(6) to net 'shutdown_HP0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP0_FPD/m_axi_rid'(1) to net 'shutdown_HP0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_awid'(6) to net 'shutdown_HP2_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_bid'(1) to net 'shutdown_HP2_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp4_arid'(6) to net 'shutdown_HP2_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_HP2_FPD/m_axi_rid'(1) to net 'shutdown_HP2_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_awid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_AWID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_bid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_BID'(6) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/ps_e_0/saxigp6_arid'(6) to net 'pr_axi_shutdown_mana_0_M_AXI_ARID'(1) - Only lower order bits will be connected. | |
| WARNING: [BD 41-235] Width mismatch when connecting pin: '/shutdown_LPD/m_axi_rid'(1) to net 'pr_axi_shutdown_mana_0_M_AXI_RID'(6) - Only lower order bits will be connected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod0_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_intr_ack/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/mb_iop_pmod1_reset/Din'(4) to net 'zynq_us_emio_gpio_o'(95) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected. | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/sim/base.v | |
| VHDL Output written to : /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hdl/base_wrapper.v | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_intc_0 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/xbar . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_0 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_1 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/tier2_xbar_2 . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i00_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_0/base_auto_pc_0_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i00_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i02_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_1/base_auto_pc_1_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/i02_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m07_couplers/auto_cc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_cc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_2/base_auto_pc_2_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m08_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_cc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_3/base_auto_pc_3_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m09_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_cc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_4/base_auto_pc_4_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m10_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m11_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m12_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m13_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_5/base_auto_pc_5_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m13_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m14_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_6/base_auto_pc_6_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m14_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m15_couplers/auto_ds . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_7/base_auto_pc_7_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m15_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m16_couplers/auto_cc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect/m18_couplers/auto_cc . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/xbar . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s00_couplers/auto_us . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/s01_couplers/auto_us . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_8/base_auto_pc_8_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_pc . | |
| WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_ooc.xdc' | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_interconnect_0/m00_couplers/auto_us . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block axi_register_slice_0 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block fmch_axi_iic . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_btns . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_leds . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block gpio_sws . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/dff_en_reset_vector_0 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/gpio . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/iic . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intc . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/intr_concat . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/io_switch . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/dlmb_v10 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/ilmb_v10 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/lmb_bram . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/lmb/lmb_bram_if_cntlr . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/logic_1 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/mb_bram_ctrl . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/xbar . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.ARUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'S_AXI.RUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice . | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.ID_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.AWUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.WUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| WARNING: [IP_Flow 19-5378] Port width mismatch for bus parameter 'M_AXI.BUSER_WIDTH'. Logical port width '0' and physical port width '1' do not match. | |
| INFO: [Common 17-14] Message 'IP_Flow 19-5378' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/microblaze_0_axi_periph/s00_mmu . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/rst_clk_wiz_1_100M . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/spi . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod0/timer . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/dff_en_reset_vector_0 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/gpio . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/iic . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intc . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intr . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/intr_concat . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/io_switch . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/dlmb_v10 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/ilmb_v10 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/lmb_bram . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/lmb/lmb_bram_if_cntlr . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/logic_1 . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/mb . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/mb_bram_ctrl . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/xbar . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice . | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created. | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/microblaze_0_axi_periph/s00_mmu . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/rst_clk_wiz_1_100M . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/spi . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block iop_pmod1/timer . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_intr_ack . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod0_reset . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod1_intr_ack . | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block mb_iop_pmod1_reset . | |
| INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e | |
| INFO: [BD 41-1029] Generation completed for the IP Integrator block mdm . | |
| INFO: [Common 17-14] Message 'BD 41-1029' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] base_ps_e_0_0: | |
| Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto. | |
| This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your | |
| design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option. | |
| The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow. | |
| For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows | |
| INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_LPD'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP2_FPD'. A default connection has been created. | |
| WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_LPD'. A default connection has been created. | |
| WARNING: [IP_Flow 19-650] IP license key '[email protected]' is enabled with a Design_Linking license. | |
| WARNING: [IP_Flow 19-650] IP license key '[email protected]' is enabled with a Design_Linking license. | |
| Exporting to file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/hw_handoff/base_frontend_0.hwh | |
| Generated Block Design Tcl file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/hw_handoff/base_frontend_0_bd.tcl | |
| Generated Hardware Definition File /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/synth/base_frontend_0.hwdef | |
| WARNING: [IP_Flow 19-650] IP license key '[email protected]' is enabled with a Design_Linking license. | |
| WARNING: [IP_Flow 19-650] IP license key '[email protected]' is enabled with a Design_Linking license. | |
| Exporting to file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/hw_handoff/base_frontend_1.hwh | |
| Generated Block Design Tcl file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/hw_handoff/base_frontend_1_bd.tcl | |
| Generated Hardware Definition File /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/synth/base_frontend_1.hwdef | |
| Exporting to file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hw_handoff/base.hwh | |
| Generated Block Design Tcl file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/hw_handoff/base_bd.tcl | |
| Generated Hardware Definition File /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/synth/base.hwdef | |
| [Fri Nov 1 16:50:54 2019] Launched base_auto_us_2_synth_1, base_auto_pc_8_synth_1, base_auto_us_0_synth_1, base_auto_ds_3_synth_1, base_auto_cc_2_synth_1, base_auto_pc_2_synth_1, base_auto_cc_3_synth_1, base_auto_pc_3_synth_1, base_auto_ds_4_synth_1, base_auto_pc_4_synth_1, base_auto_cc_0_synth_1, base_auto_pc_7_synth_1, base_auto_ds_9_synth_1, base_auto_pc_6_synth_1, base_auto_ds_8_synth_1, base_auto_pc_5_synth_1, base_auto_ds_7_synth_1, base_auto_ds_6_synth_1, base_auto_ds_5_synth_1, base_auto_cc_1_synth_1, base_auto_ds_2_synth_1, base_auto_cc_4_synth_1, base_auto_cc_5_synth_1, base_xbar_1_synth_1, base_auto_us_1_synth_1, base_xbar_0_synth_1, base_axi_intc_0_0_synth_1, base_auto_ds_1_synth_1, base_tier2_xbar_1_0_synth_1, base_tier2_xbar_2_0_synth_1, base_auto_ds_0_synth_1, base_tier2_xbar_0_0_synth_1, base_auto_pc_0_synth_1, base_auto_pc_1_synth_1, base_axi_register_slice_0_0_synth_1, base_fmch_axi_iic_0_synth_1, base_gpio_btns_0_synth_1, base_gpio_leds_0_synth_1, base_gpio_sws_0_synth_1, base_dff_en_reset_vector_0_0_synth_1, base_gpio_0_synth_1, base_iic_0_synth_1, base_intc_0_synth_1, base_intr_0_synth_1, base_io_switch_0_synth_1, base_dlmb_v10_0_synth_1, base_ilmb_v10_0_synth_1, base_lmb_bram_0_synth_1, base_lmb_bram_if_cntlr_0_synth_1, base_mb_0_synth_1, base_mb_bram_ctrl_0_synth_1, base_xbar_2_synth_1, base_s00_regslice_2_synth_1, base_m00_regslice_2_synth_1, base_m01_regslice_2_synth_1, base_m02_regslice_2_synth_1, base_m03_regslice_2_synth_1, base_m04_regslice_2_synth_1, base_m05_regslice_2_synth_1, base_m06_regslice_2_synth_1, base_m07_regslice_2_synth_1, base_s00_mmu_0_synth_1, base_rst_clk_wiz_1_100M_0_synth_1, base_spi_0_synth_1, base_timer_0_synth_1, base_dff_en_reset_vector_0_1_synth_1, base_gpio_1_synth_1, base_iic_1_synth_1, base_intc_1_synth_1, base_intr_1_synth_1, base_io_switch_1_synth_1, base_dlmb_v10_1_synth_1, base_ilmb_v10_1_synth_1, base_lmb_bram_1_synth_1, base_lmb_bram_if_cntlr_1_synth_1, base_mb_1_synth_1, base_mb_bram_ctrl_1_synth_1, base_xbar_3_synth_1, base_s00_regslice_3_synth_1, base_m00_regslice_3_synth_1, base_m01_regslice_3_synth_1, base_m02_regslice_3_synth_1, base_m03_regslice_3_synth_1, base_m04_regslice_3_synth_1, base_m05_regslice_3_synth_1, base_m06_regslice_3_synth_1, base_m07_regslice_3_synth_1, base_s00_mmu_1_synth_1, base_rst_clk_wiz_1_100M_1_synth_1, base_spi_1_synth_1, base_timer_1_synth_1, base_mdm_0_synth_1, base_pmod0_buf_0_synth_1, base_pmod1_buf_0_synth_1, base_proc_sys_reset_0_0_synth_1, base_proc_sys_reset_1_0_synth_1, base_proc_sys_reset_2_0_synth_1, base_proc_sys_reset_3_0_synth_1, base_ps_e_0_0_synth_1, base_reset_control_0_synth_1, base_shutdown_HP0_FPD_0_synth_1, base_shutdown_HP2_FPD_0_synth_1, base_shutdown_LPD_0_synth_1, base_axi_vdma_0_synth_1, base_color_convert_0_synth_1, base_frontend_0_synth_1, base_pixel_pack_0_synth_1, base_pixel_reorder_0_synth_1, base_rx_video_axis_reg_slice_0_synth_1, base_color_convert_1_synth_1, base_frontend_1_synth_1, base_pixel_reorder_1_synth_1, base_pixel_unpack_0_synth_1, base_tx_video_axis_reg_slice_0_synth_1, base_dru_ibufds_gt_odiv2_0_synth_1, base_gt_refclk_buf_0_synth_1, base_vid_phy_controller_0_synth_1, bd_20f1_v_hdmi_rx_0_synth_1, bd_20f1_v_vid_in_axi4s_0_synth_1, bd_20f1_inverter_1_0_synth_1, bd_e030_v_hdmi_tx_0_synth_1, bd_e030_v_tc_0_synth_1, bd_e030_v_axi4s_vid_out_0_synth_1, bd_e030_util_vector_logic_0_0_synth_1, bd_e030_axi_crossbar_0_synth_1, synth_1... | |
| Run output will be captured here: | |
| base_auto_us_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_us_2_synth_1/runme.log | |
| base_auto_pc_8_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_8_synth_1/runme.log | |
| base_auto_us_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_us_0_synth_1/runme.log | |
| base_auto_ds_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_3_synth_1/runme.log | |
| base_auto_cc_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_2_synth_1/runme.log | |
| base_auto_pc_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_2_synth_1/runme.log | |
| base_auto_cc_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_3_synth_1/runme.log | |
| base_auto_pc_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_3_synth_1/runme.log | |
| base_auto_ds_4_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_4_synth_1/runme.log | |
| base_auto_pc_4_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_4_synth_1/runme.log | |
| base_auto_cc_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_0_synth_1/runme.log | |
| base_auto_pc_7_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_7_synth_1/runme.log | |
| base_auto_ds_9_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_9_synth_1/runme.log | |
| base_auto_pc_6_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_6_synth_1/runme.log | |
| base_auto_ds_8_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_8_synth_1/runme.log | |
| base_auto_pc_5_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_5_synth_1/runme.log | |
| base_auto_ds_7_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_7_synth_1/runme.log | |
| base_auto_ds_6_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_6_synth_1/runme.log | |
| base_auto_ds_5_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_5_synth_1/runme.log | |
| base_auto_cc_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_1_synth_1/runme.log | |
| base_auto_ds_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_2_synth_1/runme.log | |
| base_auto_cc_4_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_4_synth_1/runme.log | |
| base_auto_cc_5_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_cc_5_synth_1/runme.log | |
| base_xbar_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_xbar_1_synth_1/runme.log | |
| base_auto_us_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_us_1_synth_1/runme.log | |
| base_xbar_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_xbar_0_synth_1/runme.log | |
| base_axi_intc_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_axi_intc_0_0_synth_1/runme.log | |
| base_auto_ds_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_1_synth_1/runme.log | |
| base_tier2_xbar_1_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_tier2_xbar_1_0_synth_1/runme.log | |
| base_tier2_xbar_2_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_tier2_xbar_2_0_synth_1/runme.log | |
| base_auto_ds_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_ds_0_synth_1/runme.log | |
| base_tier2_xbar_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_tier2_xbar_0_0_synth_1/runme.log | |
| base_auto_pc_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_0_synth_1/runme.log | |
| base_auto_pc_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_auto_pc_1_synth_1/runme.log | |
| base_axi_register_slice_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_axi_register_slice_0_0_synth_1/runme.log | |
| base_fmch_axi_iic_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_fmch_axi_iic_0_synth_1/runme.log | |
| base_gpio_btns_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gpio_btns_0_synth_1/runme.log | |
| base_gpio_leds_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gpio_leds_0_synth_1/runme.log | |
| base_gpio_sws_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gpio_sws_0_synth_1/runme.log | |
| base_dff_en_reset_vector_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_dff_en_reset_vector_0_0_synth_1/runme.log | |
| base_gpio_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gpio_0_synth_1/runme.log | |
| base_iic_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_iic_0_synth_1/runme.log | |
| base_intc_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_intc_0_synth_1/runme.log | |
| base_intr_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_intr_0_synth_1/runme.log | |
| base_io_switch_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_io_switch_0_synth_1/runme.log | |
| base_dlmb_v10_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_dlmb_v10_0_synth_1/runme.log | |
| base_ilmb_v10_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_ilmb_v10_0_synth_1/runme.log | |
| base_lmb_bram_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_lmb_bram_0_synth_1/runme.log | |
| base_lmb_bram_if_cntlr_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_lmb_bram_if_cntlr_0_synth_1/runme.log | |
| base_mb_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_mb_0_synth_1/runme.log | |
| base_mb_bram_ctrl_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_mb_bram_ctrl_0_synth_1/runme.log | |
| base_xbar_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_xbar_2_synth_1/runme.log | |
| base_s00_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_s00_regslice_2_synth_1/runme.log | |
| base_m00_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m00_regslice_2_synth_1/runme.log | |
| base_m01_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m01_regslice_2_synth_1/runme.log | |
| base_m02_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m02_regslice_2_synth_1/runme.log | |
| base_m03_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m03_regslice_2_synth_1/runme.log | |
| base_m04_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m04_regslice_2_synth_1/runme.log | |
| base_m05_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m05_regslice_2_synth_1/runme.log | |
| base_m06_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m06_regslice_2_synth_1/runme.log | |
| base_m07_regslice_2_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m07_regslice_2_synth_1/runme.log | |
| base_s00_mmu_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_s00_mmu_0_synth_1/runme.log | |
| base_rst_clk_wiz_1_100M_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_rst_clk_wiz_1_100M_0_synth_1/runme.log | |
| base_spi_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_spi_0_synth_1/runme.log | |
| base_timer_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_timer_0_synth_1/runme.log | |
| base_dff_en_reset_vector_0_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_dff_en_reset_vector_0_1_synth_1/runme.log | |
| base_gpio_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gpio_1_synth_1/runme.log | |
| base_iic_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_iic_1_synth_1/runme.log | |
| base_intc_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_intc_1_synth_1/runme.log | |
| base_intr_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_intr_1_synth_1/runme.log | |
| base_io_switch_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_io_switch_1_synth_1/runme.log | |
| base_dlmb_v10_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_dlmb_v10_1_synth_1/runme.log | |
| base_ilmb_v10_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_ilmb_v10_1_synth_1/runme.log | |
| base_lmb_bram_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_lmb_bram_1_synth_1/runme.log | |
| base_lmb_bram_if_cntlr_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_lmb_bram_if_cntlr_1_synth_1/runme.log | |
| base_mb_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_mb_1_synth_1/runme.log | |
| base_mb_bram_ctrl_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_mb_bram_ctrl_1_synth_1/runme.log | |
| base_xbar_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_xbar_3_synth_1/runme.log | |
| base_s00_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_s00_regslice_3_synth_1/runme.log | |
| base_m00_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m00_regslice_3_synth_1/runme.log | |
| base_m01_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m01_regslice_3_synth_1/runme.log | |
| base_m02_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m02_regslice_3_synth_1/runme.log | |
| base_m03_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m03_regslice_3_synth_1/runme.log | |
| base_m04_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m04_regslice_3_synth_1/runme.log | |
| base_m05_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m05_regslice_3_synth_1/runme.log | |
| base_m06_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m06_regslice_3_synth_1/runme.log | |
| base_m07_regslice_3_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_m07_regslice_3_synth_1/runme.log | |
| base_s00_mmu_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_s00_mmu_1_synth_1/runme.log | |
| base_rst_clk_wiz_1_100M_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_rst_clk_wiz_1_100M_1_synth_1/runme.log | |
| base_spi_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_spi_1_synth_1/runme.log | |
| base_timer_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_timer_1_synth_1/runme.log | |
| base_mdm_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_mdm_0_synth_1/runme.log | |
| base_pmod0_buf_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pmod0_buf_0_synth_1/runme.log | |
| base_pmod1_buf_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pmod1_buf_0_synth_1/runme.log | |
| base_proc_sys_reset_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_proc_sys_reset_0_0_synth_1/runme.log | |
| base_proc_sys_reset_1_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_proc_sys_reset_1_0_synth_1/runme.log | |
| base_proc_sys_reset_2_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_proc_sys_reset_2_0_synth_1/runme.log | |
| base_proc_sys_reset_3_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_proc_sys_reset_3_0_synth_1/runme.log | |
| base_ps_e_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_ps_e_0_0_synth_1/runme.log | |
| base_reset_control_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_reset_control_0_synth_1/runme.log | |
| base_shutdown_HP0_FPD_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_shutdown_HP0_FPD_0_synth_1/runme.log | |
| base_shutdown_HP2_FPD_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_shutdown_HP2_FPD_0_synth_1/runme.log | |
| base_shutdown_LPD_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_shutdown_LPD_0_synth_1/runme.log | |
| base_axi_vdma_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_axi_vdma_0_synth_1/runme.log | |
| base_color_convert_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_color_convert_0_synth_1/runme.log | |
| base_frontend_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_frontend_0_synth_1/runme.log | |
| base_pixel_pack_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pixel_pack_0_synth_1/runme.log | |
| base_pixel_reorder_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pixel_reorder_0_synth_1/runme.log | |
| base_rx_video_axis_reg_slice_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_rx_video_axis_reg_slice_0_synth_1/runme.log | |
| base_color_convert_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_color_convert_1_synth_1/runme.log | |
| base_frontend_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_frontend_1_synth_1/runme.log | |
| base_pixel_reorder_1_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pixel_reorder_1_synth_1/runme.log | |
| base_pixel_unpack_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_pixel_unpack_0_synth_1/runme.log | |
| base_tx_video_axis_reg_slice_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_tx_video_axis_reg_slice_0_synth_1/runme.log | |
| base_dru_ibufds_gt_odiv2_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_dru_ibufds_gt_odiv2_0_synth_1/runme.log | |
| base_gt_refclk_buf_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_gt_refclk_buf_0_synth_1/runme.log | |
| base_vid_phy_controller_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/base_vid_phy_controller_0_synth_1/runme.log | |
| bd_20f1_v_hdmi_rx_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_20f1_v_hdmi_rx_0_synth_1/runme.log | |
| bd_20f1_v_vid_in_axi4s_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_20f1_v_vid_in_axi4s_0_synth_1/runme.log | |
| bd_20f1_inverter_1_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_20f1_inverter_1_0_synth_1/runme.log | |
| bd_e030_v_hdmi_tx_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_v_hdmi_tx_0_synth_1/runme.log | |
| bd_e030_v_tc_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_v_tc_0_synth_1/runme.log | |
| bd_e030_v_axi4s_vid_out_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_v_axi4s_vid_out_0_synth_1/runme.log | |
| bd_e030_util_vector_logic_0_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_util_vector_logic_0_0_synth_1/runme.log | |
| bd_e030_axi_crossbar_0_synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_axi_crossbar_0_synth_1/runme.log | |
| synth_1: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/synth_1/runme.log | |
| [Fri Nov 1 16:50:54 2019] Launched impl_1... | |
| Run output will be captured here: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/runme.log | |
| launch_runs: Time (s): cpu = 00:00:54 ; elapsed = 00:01:03 . Memory (MB): peak = 4060.629 ; gain = 2324.430 ; free physical = 169 ; free virtual = 13797 | |
| [Fri Nov 1 16:50:54 2019] Waiting for impl_1 to finish... | |
| *** Running vivado | |
| with args -log base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source base_wrapper.tcl -notrace | |
| ****** Vivado v2019.1 (64-bit) | |
| **** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019 | |
| **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
| ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. | |
| source base_wrapper.tcl -notrace | |
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |
| INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ip'. | |
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2019.1/data/ip'. | |
| add_files: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1481.641 ; gain = 82.848 ; free physical = 8651 ; free virtual = 13704 | |
| Command: link_design -top base_wrapper -part xczu7ev-ffvc1156-2-e | |
| Design is defaulting to srcset: sources_1 | |
| Design is defaulting to constrset: constrs_1 | |
| INFO: [Device 21-403] Loading part xczu7ev-ffvc1156-2-e | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.dcp' for cell 'base_i/axi_intc_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_register_slice_0_0/base_axi_register_slice_0_0.dcp' for cell 'base_i/axi_register_slice_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0.dcp' for cell 'base_i/fmch_axi_iic' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.dcp' for cell 'base_i/gpio_btns' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.dcp' for cell 'base_i/gpio_leds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.dcp' for cell 'base_i/gpio_sws' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.dcp' for cell 'base_i/mdm' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0.dcp' for cell 'base_i/pmod0_buf' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0.dcp' for cell 'base_i/pmod1_buf' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.dcp' for cell 'base_i/proc_sys_reset_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.dcp' for cell 'base_i/proc_sys_reset_1' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.dcp' for cell 'base_i/proc_sys_reset_2' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.dcp' for cell 'base_i/proc_sys_reset_3' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.dcp' for cell 'base_i/ps_e_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.dcp' for cell 'base_i/reset_control' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_HP0_FPD_0/base_shutdown_HP0_FPD_0.dcp' for cell 'base_i/shutdown_HP0_FPD' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_HP2_FPD_0/base_shutdown_HP2_FPD_0.dcp' for cell 'base_i/shutdown_HP2_FPD' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_shutdown_LPD_0/base_shutdown_LPD_0.dcp' for cell 'base_i/shutdown_LPD' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_0_0/base_tier2_xbar_0_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_1_0/base_tier2_xbar_1_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_1' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tier2_xbar_2_0/base_tier2_xbar_2_0.dcp' for cell 'base_i/axi_interconnect/tier2_xbar_2' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_0/base_xbar_0.dcp' for cell 'base_i/axi_interconnect/xbar' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0.dcp' for cell 'base_i/axi_interconnect/i00_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_0/base_auto_pc_0.dcp' for cell 'base_i/axi_interconnect/i00_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1.dcp' for cell 'base_i/axi_interconnect/i02_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_1/base_auto_pc_1.dcp' for cell 'base_i/axi_interconnect/i02_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0.dcp' for cell 'base_i/axi_interconnect/m07_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_2/base_auto_pc_2.dcp' for cell 'base_i/axi_interconnect/m08_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_3/base_auto_pc_3.dcp' for cell 'base_i/axi_interconnect/m09_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_4/base_auto_pc_4.dcp' for cell 'base_i/axi_interconnect/m10_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5.dcp' for cell 'base_i/axi_interconnect/m11_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6.dcp' for cell 'base_i/axi_interconnect/m12_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7.dcp' for cell 'base_i/axi_interconnect/m13_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_5/base_auto_pc_5.dcp' for cell 'base_i/axi_interconnect/m13_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8.dcp' for cell 'base_i/axi_interconnect/m14_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_6/base_auto_pc_6.dcp' for cell 'base_i/axi_interconnect/m14_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9.dcp' for cell 'base_i/axi_interconnect/m15_couplers/auto_ds' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_7/base_auto_pc_7.dcp' for cell 'base_i/axi_interconnect/m15_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4.dcp' for cell 'base_i/axi_interconnect/m16_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5.dcp' for cell 'base_i/axi_interconnect/m18_couplers/auto_cc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_1/base_xbar_1.dcp' for cell 'base_i/axi_interconnect_0/xbar' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_pc_8/base_auto_pc_8.dcp' for cell 'base_i/axi_interconnect_0/m00_couplers/auto_pc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0.dcp' for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1.dcp' for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2.dcp' for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dff_en_reset_vector_0_0/base_dff_en_reset_vector_0_0.dcp' for cell 'base_i/iop_pmod0/dff_en_reset_vector_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.dcp' for cell 'base_i/iop_pmod0/gpio' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0.dcp' for cell 'base_i/iop_pmod0/iic' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.dcp' for cell 'base_i/iop_pmod0/intc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.dcp' for cell 'base_i/iop_pmod0/intr' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_io_switch_0/base_io_switch_0.dcp' for cell 'base_i/iop_pmod0/io_switch' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.dcp' for cell 'base_i/iop_pmod0/mb' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_bram_ctrl_0/base_mb_bram_ctrl_0.dcp' for cell 'base_i/iop_pmod0/mb_bram_ctrl' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.dcp' for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.dcp' for cell 'base_i/iop_pmod0/spi' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.dcp' for cell 'base_i/iop_pmod0/timer' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_0/base_dlmb_v10_0.dcp' for cell 'base_i/iop_pmod0/lmb/dlmb_v10' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_0/base_ilmb_v10_0.dcp' for cell 'base_i/iop_pmod0/lmb/ilmb_v10' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_0/base_lmb_bram_0.dcp' for cell 'base_i/iop_pmod0/lmb/lmb_bram' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_if_cntlr_0/base_lmb_bram_if_cntlr_0.dcp' for cell 'base_i/iop_pmod0/lmb/lmb_bram_if_cntlr' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_mmu_0/base_s00_mmu_0.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_mmu' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_2/base_xbar_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/xbar' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2.dcp' for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dff_en_reset_vector_0_1/base_dff_en_reset_vector_0_1.dcp' for cell 'base_i/iop_pmod1/dff_en_reset_vector_0' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.dcp' for cell 'base_i/iop_pmod1/gpio' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1.dcp' for cell 'base_i/iop_pmod1/iic' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.dcp' for cell 'base_i/iop_pmod1/intc' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.dcp' for cell 'base_i/iop_pmod1/intr' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_io_switch_1/base_io_switch_1.dcp' for cell 'base_i/iop_pmod1/io_switch' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.dcp' for cell 'base_i/iop_pmod1/mb' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_bram_ctrl_1/base_mb_bram_ctrl_1.dcp' for cell 'base_i/iop_pmod1/mb_bram_ctrl' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.dcp' for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.dcp' for cell 'base_i/iop_pmod1/spi' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.dcp' for cell 'base_i/iop_pmod1/timer' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_1/base_dlmb_v10_1.dcp' for cell 'base_i/iop_pmod1/lmb/dlmb_v10' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_1/base_ilmb_v10_1.dcp' for cell 'base_i/iop_pmod1/lmb/ilmb_v10' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_1/base_lmb_bram_1.dcp' for cell 'base_i/iop_pmod1/lmb/lmb_bram' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_lmb_bram_if_cntlr_1/base_lmb_bram_if_cntlr_1.dcp' for cell 'base_i/iop_pmod1/lmb/lmb_bram_if_cntlr' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_mmu_1/base_s00_mmu_1.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/s00_mmu' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_xbar_3/base_xbar_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/xbar' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice' | |
| INFO: [Project 1-454] Reading design checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3.dcp' for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice' | |
| INFO: [Common 17-14] Message 'Project 1-454' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| INFO: [Netlist 29-17] Analyzing 2614 Unisim elements for replacement | |
| INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds | |
| INFO: [Project 1-479] Netlist was created with Vivado 2019.1 | |
| INFO: [Project 1-570] Preparing netlist for logic optimization | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_O[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod0_buf/IOBUF_IO_T[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[1]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[2]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[3]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[4]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[5]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[6]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_I[7]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'SLEW' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[0]' is not directly connected to top level port. Synthesis is ignored for SLEW but preserved for implementation. | |
| WARNING: [Constraints 18-550] Could not create 'DRIVE' constraint because net 'base_i/pmod1_buf/IOBUF_IO_O[1]' is not directly connected to top level port. Synthesis is ignored for DRIVE but preserved for implementation. | |
| INFO: [Common 17-14] Message 'Constraints 18-550' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.xdc] for cell 'base_i/axi_intc_0/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0.xdc] for cell 'base_i/axi_intc_0/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0_board.xdc] for cell 'base_i/fmch_axi_iic/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_fmch_axi_iic_0/base_fmch_axi_iic_0_board.xdc] for cell 'base_i/fmch_axi_iic/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0_board.xdc] for cell 'base_i/gpio_btns/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0_board.xdc] for cell 'base_i/gpio_btns/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.xdc] for cell 'base_i/gpio_btns/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_btns_0/base_gpio_btns_0.xdc] for cell 'base_i/gpio_btns/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0_board.xdc] for cell 'base_i/gpio_leds/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0_board.xdc] for cell 'base_i/gpio_leds/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.xdc] for cell 'base_i/gpio_leds/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_leds_0/base_gpio_leds_0.xdc] for cell 'base_i/gpio_leds/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0_board.xdc] for cell 'base_i/gpio_sws/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0_board.xdc] for cell 'base_i/gpio_sws/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.xdc] for cell 'base_i/gpio_sws/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_sws_0/base_gpio_sws_0.xdc] for cell 'base_i/gpio_sws/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0_board.xdc] for cell 'base_i/iop_pmod0/gpio/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0_board.xdc] for cell 'base_i/iop_pmod0/gpio/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.xdc] for cell 'base_i/iop_pmod0/gpio/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_0/base_gpio_0.xdc] for cell 'base_i/iop_pmod0/gpio/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0_board.xdc] for cell 'base_i/iop_pmod0/iic/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_0/base_iic_0_board.xdc] for cell 'base_i/iop_pmod0/iic/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.xdc] for cell 'base_i/iop_pmod0/intc/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0.xdc] for cell 'base_i/iop_pmod0/intc/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0_board.xdc] for cell 'base_i/iop_pmod0/intr/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0_board.xdc] for cell 'base_i/iop_pmod0/intr/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.xdc] for cell 'base_i/iop_pmod0/intr/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_0/base_intr_0.xdc] for cell 'base_i/iop_pmod0/intr/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_0/base_dlmb_v10_0.xdc] for cell 'base_i/iop_pmod0/lmb/dlmb_v10/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_0/base_dlmb_v10_0.xdc] for cell 'base_i/iop_pmod0/lmb/dlmb_v10/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_0/base_ilmb_v10_0.xdc] for cell 'base_i/iop_pmod0/lmb/ilmb_v10/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_0/base_ilmb_v10_0.xdc] for cell 'base_i/iop_pmod0/lmb/ilmb_v10/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.xdc] for cell 'base_i/iop_pmod0/mb/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/base_mb_0.xdc] for cell 'base_i/iop_pmod0/mb/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0_board.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0_board.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_0/base_rst_clk_wiz_1_100M_0.xdc] for cell 'base_i/iop_pmod0/rst_clk_wiz_1_100M/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_board.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_board.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.xdc] for cell 'base_i/iop_pmod0/timer/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_0/base_timer_0.xdc] for cell 'base_i/iop_pmod0/timer/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1_board.xdc] for cell 'base_i/iop_pmod1/gpio/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1_board.xdc] for cell 'base_i/iop_pmod1/gpio/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.xdc] for cell 'base_i/iop_pmod1/gpio/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gpio_1/base_gpio_1.xdc] for cell 'base_i/iop_pmod1/gpio/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1_board.xdc] for cell 'base_i/iop_pmod1/iic/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_iic_1/base_iic_1_board.xdc] for cell 'base_i/iop_pmod1/iic/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.xdc] for cell 'base_i/iop_pmod1/intc/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1.xdc] for cell 'base_i/iop_pmod1/intc/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1_board.xdc] for cell 'base_i/iop_pmod1/intr/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1_board.xdc] for cell 'base_i/iop_pmod1/intr/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.xdc] for cell 'base_i/iop_pmod1/intr/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intr_1/base_intr_1.xdc] for cell 'base_i/iop_pmod1/intr/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_1/base_dlmb_v10_1.xdc] for cell 'base_i/iop_pmod1/lmb/dlmb_v10/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dlmb_v10_1/base_dlmb_v10_1.xdc] for cell 'base_i/iop_pmod1/lmb/dlmb_v10/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_1/base_ilmb_v10_1.xdc] for cell 'base_i/iop_pmod1/lmb/ilmb_v10/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ilmb_v10_1/base_ilmb_v10_1.xdc] for cell 'base_i/iop_pmod1/lmb/ilmb_v10/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.xdc] for cell 'base_i/iop_pmod1/mb/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/base_mb_1.xdc] for cell 'base_i/iop_pmod1/mb/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1_board.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1_board.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rst_clk_wiz_1_100M_1/base_rst_clk_wiz_1_100M_1.xdc] for cell 'base_i/iop_pmod1/rst_clk_wiz_1_100M/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_board.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_board.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.xdc] for cell 'base_i/iop_pmod1/timer/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_timer_1/base_timer_1.xdc] for cell 'base_i/iop_pmod1/timer/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc] for cell 'base_i/mdm/U0' | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc:51] | |
| get_clocks: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 3831.512 ; gain = 570.492 ; free physical = 6418 ; free virtual = 11472 | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mdm_0/base_mdm_0.xdc] for cell 'base_i/mdm/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0_board.xdc] for cell 'base_i/pmod0_buf/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod0_buf_0/base_pmod0_buf_0_board.xdc] for cell 'base_i/pmod0_buf/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0_board.xdc] for cell 'base_i/pmod1_buf/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_pmod1_buf_0/base_pmod1_buf_0_board.xdc] for cell 'base_i/pmod1_buf/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0_board.xdc] for cell 'base_i/proc_sys_reset_0/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0_board.xdc] for cell 'base_i/proc_sys_reset_0/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.xdc] for cell 'base_i/proc_sys_reset_0/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_0_0/base_proc_sys_reset_0_0.xdc] for cell 'base_i/proc_sys_reset_0/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0_board.xdc] for cell 'base_i/proc_sys_reset_1/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0_board.xdc] for cell 'base_i/proc_sys_reset_1/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.xdc] for cell 'base_i/proc_sys_reset_1/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_1_0/base_proc_sys_reset_1_0.xdc] for cell 'base_i/proc_sys_reset_1/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0_board.xdc] for cell 'base_i/proc_sys_reset_2/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0_board.xdc] for cell 'base_i/proc_sys_reset_2/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.xdc] for cell 'base_i/proc_sys_reset_2/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_2_0/base_proc_sys_reset_2_0.xdc] for cell 'base_i/proc_sys_reset_2/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0_board.xdc] for cell 'base_i/proc_sys_reset_3/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0_board.xdc] for cell 'base_i/proc_sys_reset_3/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.xdc] for cell 'base_i/proc_sys_reset_3/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_proc_sys_reset_3_0/base_proc_sys_reset_3_0.xdc] for cell 'base_i/proc_sys_reset_3/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.xdc] for cell 'base_i/ps_e_0/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_ps_e_0_0/base_ps_e_0_0.xdc] for cell 'base_i/ps_e_0/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0_board.xdc] for cell 'base_i/reset_control/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0_board.xdc] for cell 'base_i/reset_control/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.xdc] for cell 'base_i/reset_control/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_reset_control_0/base_reset_control_0.xdc] for cell 'base_i/reset_control/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc] for cell 'base_i/video/axi_vdma/U0' | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:68] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:72] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:76] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:80] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:84] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:88] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:92] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:96] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-4' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:100] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:176] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:180] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:184] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:188] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:192] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:196] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:200] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-6' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc:204] | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0.xdc] for cell 'base_i/video/axi_vdma/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dru_ibufds_gt_odiv2_0/base_dru_ibufds_gt_odiv2_0_board.xdc] for cell 'base_i/video/phy/dru_ibufds_gt_odiv2/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_dru_ibufds_gt_odiv2_0/base_dru_ibufds_gt_odiv2_0_board.xdc] for cell 'base_i/video/phy/dru_ibufds_gt_odiv2/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gt_refclk_buf_0/base_gt_refclk_buf_0_board.xdc] for cell 'base_i/video/phy/gt_refclk_buf/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_gt_refclk_buf_0/base_gt_refclk_buf_0_board.xdc] for cell 'base_i/video/phy/gt_refclk_buf/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/vid_phy_controller_xdc.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/vid_phy_controller_xdc.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/ip_0/synth/base_vid_phy_controller_0_gtwrapper.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_wrapper_inst/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/ip_0/synth/base_vid_phy_controller_0_gtwrapper.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_wrapper_inst/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/constrs_1/imports/constraints/base.xdc] | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/constrs_1/imports/constraints/base.xdc] | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0_clocks.xdc] for cell 'base_i/axi_intc_0/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_intc_0_0/base_axi_intc_0_0_clocks.xdc] for cell 'base_i/axi_intc_0/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_clocks.xdc] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_0/base_auto_ds_0_clocks.xdc] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_clocks.xdc] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_1/base_auto_ds_1_clocks.xdc] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst' | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:7] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:10] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc:13] | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_0/base_auto_cc_0_clocks.xdc] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_1/base_auto_cc_1_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_2/base_auto_ds_2_clocks.xdc] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_2/base_auto_cc_2_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_3/base_auto_ds_3_clocks.xdc] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_3/base_auto_cc_3_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_4/base_auto_ds_4_clocks.xdc] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_clocks.xdc] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_5/base_auto_ds_5_clocks.xdc] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_clocks.xdc] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_6/base_auto_ds_6_clocks.xdc] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_clocks.xdc] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_7/base_auto_ds_7_clocks.xdc] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_clocks.xdc] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_8/base_auto_ds_8_clocks.xdc] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_clocks.xdc] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_ds_9/base_auto_ds_9_clocks.xdc] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst' | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:7] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:10] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc:13] | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_4/base_auto_cc_4_clocks.xdc] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst' | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:7] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:10] | |
| WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-15' -to list should not be empty. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc:13] | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_cc_5/base_auto_cc_5_clocks.xdc] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_clocks.xdc] for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_1/base_auto_us_1_clocks.xdc] for cell 'base_i/axi_interconnect_0/s00_couplers/auto_us/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_clocks.xdc] for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_2/base_auto_us_2_clocks.xdc] for cell 'base_i/axi_interconnect_0/s01_couplers/auto_us/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_clocks.xdc] for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_auto_us_0/base_auto_us_0_clocks.xdc] for cell 'base_i/axi_interconnect_0/m00_couplers/auto_us/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_register_slice_0_0/base_axi_register_slice_0_0_clocks.xdc] for cell 'base_i/axi_register_slice_0/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_register_slice_0_0/base_axi_register_slice_0_0_clocks.xdc] for cell 'base_i/axi_register_slice_0/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0_clocks.xdc] for cell 'base_i/iop_pmod0/intc/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_0/base_intc_0_clocks.xdc] for cell 'base_i/iop_pmod0/intc/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_2/base_s00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_2/base_m00_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_2/base_m01_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_2/base_m02_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_2/base_m03_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_2/base_m04_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_2/base_m05_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_2/base_m06_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_2/base_m07_regslice_2_clocks.xdc] for cell 'base_i/iop_pmod0/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_clocks.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_0/base_spi_0_clocks.xdc] for cell 'base_i/iop_pmod0/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1_clocks.xdc] for cell 'base_i/iop_pmod1/intc/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_intc_1/base_intc_1_clocks.xdc] for cell 'base_i/iop_pmod1/intc/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_s00_regslice_3/base_s00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/s00_couplers/s00_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m00_regslice_3/base_m00_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m00_couplers/m00_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m01_regslice_3/base_m01_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m01_couplers/m01_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m02_regslice_3/base_m02_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m02_couplers/m02_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m03_regslice_3/base_m03_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m03_couplers/m03_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m04_regslice_3/base_m04_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m04_couplers/m04_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m05_regslice_3/base_m05_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m05_couplers/m05_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m06_regslice_3/base_m06_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m06_couplers/m06_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_m07_regslice_3/base_m07_regslice_3_clocks.xdc] for cell 'base_i/iop_pmod1/microblaze_0_axi_periph/m07_couplers/m07_regslice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_clocks.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_spi_1/base_spi_1_clocks.xdc] for cell 'base_i/iop_pmod1/spi/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0_clocks.xdc] for cell 'base_i/video/axi_vdma/U0' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_axi_vdma_0/base_axi_vdma_0_clocks.xdc] for cell 'base_i/video/axi_vdma/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_0/bd_20f1_v_hdmi_rx_0_core.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_0/bd_20f1_v_hdmi_rx_0_core.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_1/bd_20f1_v_vid_in_axi4s_0_clocks.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_0/bd_0/ip/ip_1/bd_20f1_v_vid_in_axi4s_0_clocks.xdc] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rx_video_axis_reg_slice_0/base_rx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_in/rx_video_axis_reg_slice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_rx_video_axis_reg_slice_0/base_rx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_in/rx_video_axis_reg_slice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_0/bd_e030_v_hdmi_tx_0_core.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_0/bd_e030_v_hdmi_tx_0_core.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_tc/U0' | |
| WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of [get_ports -scoped_to_current_instance clk]'. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:2] | |
| Resolution: Verify the create_clock command was called to create the clock object before it is referenced. | |
| INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:2] | |
| CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:5] | |
| Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. | |
| CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:6] | |
| CRITICAL WARNING: [Vivado 12-4739] set_max_delay:No valid object(s) found for '-to [all_registers -clock [get_clocks -of [get_ports -scoped_to_current_instance clk]]]'. [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc:6] | |
| Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_1/bd_e030_v_tc_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_tc/U0' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_2/bd_e030_v_axi4s_vid_out_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_frontend_1/bd_0/ip/ip_2/bd_e030_v_axi4s_vid_out_0_clocks.xdc] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tx_video_axis_reg_slice_0/base_tx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_out/tx_video_axis_reg_slice/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_tx_video_axis_reg_slice_0/base_tx_video_axis_reg_slice_0_clocks.xdc] for cell 'base_i/video/hdmi_out/tx_video_axis_reg_slice/inst' | |
| Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/base_vid_phy_controller_0_clocks.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' | |
| Finished Parsing XDC File [/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_vid_phy_controller_0/base_vid_phy_controller_0_clocks.xdc] for cell 'base_i/video/phy/vid_phy_controller/inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_gtwiz_reset_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxprbssel_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbssel_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Config_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_handshake_DRP_Status_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_cnt_tol_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_FREQ_CAP_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_FREQ_CAP_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_FREQ_CAP_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_FREQ_CAP_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_FREQ_CAP_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_FREQ_CAP_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| WARNING: [XPM_CDC_ARRAY_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_cpll_cal_txoutclk_period_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_VERSION_in_sync_b0gt0inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_VERSION_in_sync_b0gt0inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txdiffctrl_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxbufstatus_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_array_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txbufstatus_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/i02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m11_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m12_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m13_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m14_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/axi_interconnect/m15_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_drp_reset_RST_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_drp_reset_RST_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/LRST_XPM_ASYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/LRST_XPM_ASYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/LRST_XPM_ASYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/LRST_XPM_ASYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/LRST_XPM_ASYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/LRST_XPM_ASYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/PIX_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.DCS_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/P_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/PKT_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/HDR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SUB_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/AUD_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACR_FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/FIFO_INST/RP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m07_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m08_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m09_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.xpm_cdc_single_inst3' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.xpm_cdc_single_inst1' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.xpm_cdc_single_inst2' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m10_couplers/auto_cc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m16_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_aw/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_ar/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_fwd_w/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_b/handshake/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/axi_interconnect/m18_couplers/auto_cc/inst/gen_clock_conv.gen_async_lite_conv.clock_conv_lite_resp_r/handshake/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_pll_lock_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt2inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt2inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b02_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b02_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll1lock_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_qpll0lock_out_dly_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.rxoutclk_mmcm0_i/rx_mmcm_locked_xpm' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.rxoutclk_mmcm0_i/rx_mmcm_locked_xpm' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/rx_mmcm.RXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.txoutclk_mmcm0_i/tx_mmcm_locked_xpm' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.txoutclk_mmcm0_i/tx_mmcm_locked_xpm' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.TXPLL_DRP_INST/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TX_LOCK_CAP_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TX_LOCK_CAP_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RUN_SYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/TXCLK_RUN_SYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RUN_SYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/RXCLK_RUN_SYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RUN_SYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/clock_detector_inst/DRUCLK_RUN_SYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gtcommon_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt2_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt1_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/drp_control_b0gt0_inst/xpm_single_DRP_Rsp_Rd_Toggle_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_txpllclksel_in0_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt1_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0gt2_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' | |
| INFO: [Vivado 12-3272] Current instance is the top level cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' of design 'design_1' [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| WARNING: [XPM_CDC_SINGLE: TCL-1000] The source and destination clocks are the same. | |
| Instance: base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst | |
| This will add unnecessary latency to the design. Please check the design for the following: | |
| 1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules. | |
| 2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message. | |
| [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl:5] | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_drp_rdy_b0_common_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_mmcm_drp_locked_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_tx_mmcm_drp_locked_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_tx_done_out_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_tx_done_out_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_rx_done_out_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_gtwiz_reset_rx_done_out_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_done_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_done_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_reset_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_reset_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_start_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_start_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_error_b0_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_buffbypass_tx_error_b0_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt0inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt0inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b00_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b00_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxcdrlock_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxpolarity_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_rxprbscntreset_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt1inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_single_prbserr_out_sync_b0gt1inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txinhibit_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpolarity_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txprbsforceerr_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txelecidle_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_rxpmaresetdone_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b01_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/phy/vid_phy_controller/inst/xpm_array_single_txpmaresetdone_b01_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_ALN_LOCK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_ALN_LOCK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/LCLK_TS_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/LCLK_TS_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.VCLK_VGB_RST_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/gen_ch0.VCLK_VGB_RST_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_SCRM_EN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_SCRM_EN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_LNK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_LNK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VID_BRDG_OVERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VID_BRDG_OVERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_CLR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/LCLK_CLR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/ACLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_PRO_UPD_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_PRO_UPD_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_ACT_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_ACT_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_GCP_CD_CHG_ACK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_GCP_CD_CHG_ACK_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/LCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_HDMI_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_HDMI_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CHG_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CHG_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_PKT_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_PKT_ERR_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LCLK_VID_VSYNC_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LCLK_VID_VSYNC_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/VCLK_CTRL_FLD_POL_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/VCLK_CTRL_FLD_POL_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_HS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_HS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VTD_INST/SCLK_VID_RDY_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_EN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_EN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/SCLK_STA_SCRM_LOCK_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CD_INST/DET_SYNC_INST/XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/CD_INST/DET_SYNC_INST/XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[2].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[1].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/STA_INST/gen_err_cap[0].SCLK_LNK_ERR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_AUD_CH_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_FMT_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_N_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUD_INST/SCLK_ACR_CTS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_LNK_RST_CAP_INST/XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_LNK_RST_CAP_INST/XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_GCP_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_VIC_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/AUX_INST/SCLK_AVI_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_REMAP_OVERFLOW_INST/xpm_cdc_single_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_REMAP_OVERFLOW_INST/xpm_cdc_single_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_RESET_PULSE_INST/xpm_cdc_single_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/CDC_SINGLE_RESET_PULSE_INST/xpm_cdc_single_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_LOCKED_INST/xpm_cdc_single_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/CDC_SINGLE_REMAP_UNDERFLOW_INST/xpm_cdc_single_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/PIO_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/PIO_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ET_DIS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_RUN_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_NOISE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CTRL_REG_NOISE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_VS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_VS_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_LOCKED_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_LOCKED_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_UNDERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VID_BRDG_UNDERFLOW_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_AVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_CLEARAVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GCP_CLEARAVMUTE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SCLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/SCLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_VID_VS_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_VID_VS_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_PKT_RDY_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/ACLK_CTRL_FMT_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_RUN_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_FMT_SYNC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_CDC_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_SCRM_INST/gen_single.(null)[0].XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_MODE_SCRM_INST/gen_single.(null)[0].XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_CFG_CS_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_RV_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_GY_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/GEN_MASK.MASK_INST/VCLK_BU_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_CD_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUX_INST/LCLK_CFG_PP_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/AUD_INST/LCLK_CTRL_CH_SYNC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CFG_SR_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH0_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/VCLK_CFG_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/CORE_INST/STA_PP_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VCLK_CD_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_dest2src_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/HPD_INST/HPD_CAP_INST/XPM_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/HPD_INST/HPD_CAP_INST/XPM_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/BRDG_CDC_INST/gen_handshake.XPM_INST/xpm_cdc_single_src2dest_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/M_AXIS_VIDEO_RST_CDC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/M_AXIS_VIDEO_RST_CDC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/VIDEO_RST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/VIDEO_RST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SRST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SRST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ARST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/ARST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VRST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/VRST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_RST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/AXIS_RST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/S_AXIS_VIDEO_RST_CDC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/S_AXIS_VIDEO_RST_CDC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/LRST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/LRST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/VIDEO_RST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/VIDEO_RST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/AXIS_RST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/AXIS_RST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SRST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SRST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ARST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/ARST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VRST_INST/XPM_RST_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_sync_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst/SYS_INST/VRST_INST/XPM_RST_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP0_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_HP2_FPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_raddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wresp_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo' | |
| Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| Finished Sourcing Tcl File [/opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl] for cell 'base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo' | |
| INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod0/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[15].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell base_i/iop_pmod1/lmb/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM. | |
| Generating merged BMM file for the design top 'base_wrapper'... | |
| INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_0/data/mb_bootloop_le.elf /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/ip/base_mb_1/data/mb_bootloop_le.elf | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3868.578 ; gain = 0.000 ; free physical = 6552 ; free virtual = 11610 | |
| INFO: [Project 1-111] Unisim Transformation Summary: | |
| A total of 900 instances were transformed. | |
| DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 39 instances | |
| IBUF => IBUF (IBUFCTRL, INBUF): 12 instances | |
| IOBUF => IOBUF (IBUFCTRL, INBUF, OBUFT): 22 instances | |
| LUT6_2 => LUT6_2 (LUT5, LUT6): 160 instances | |
| OBUFTDS => OBUFTDS: 2 instances | |
| RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 32 instances | |
| RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 450 instances | |
| RAM64M8 => RAM64M8 (RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E, RAMD64E): 129 instances | |
| RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 52 instances | |
| RAM64X1S => RAM64X1S (RAMS64E): 2 instances | |
| 193 Infos, 173 Warnings, 3 Critical Warnings and 0 Errors encountered. | |
| link_design completed successfully | |
| link_design: Time (s): cpu = 00:01:13 ; elapsed = 00:01:31 . Memory (MB): peak = 3868.578 ; gain = 2386.938 ; free physical = 6555 ; free virtual = 11613 | |
| Command: opt_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' | |
| Running DRC as a precondition to command opt_design | |
| Starting DRC Task | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Project 1-461] DRC finished with 0 Errors | |
| INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |
| Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3884.527 ; gain = 15.949 ; free physical = 6541 ; free virtual = 11600 | |
| Starting Cache Timing Information Task | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Ending Cache Timing Information Task | Checksum: 706a9b5e | |
| Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3884.527 ; gain = 0.000 ; free physical = 6380 ; free virtual = 11439 | |
| Starting Logic Optimization Task | |
| Phase 1 Retarget | |
| INFO: [Opt 31-138] Pushed 203 inverter(s) to 14409 load pin(s). | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_in/color_convert/inst/ret_V_10_reg_1734_reg | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_in/color_convert/inst/ret_V_14_reg_1714_reg | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_in/color_convert/inst/ret_V_reg_1709_reg | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_out/color_convert/inst/ret_V_10_reg_1734_reg | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_out/color_convert/inst/ret_V_14_reg_1714_reg | |
| INFO: [Opt 31-925] Fixed cascade connection for DSP: base_i/video/hdmi_out/color_convert/inst/ret_V_reg_1709_reg | |
| INFO: [Opt 31-49] Retargeted 0 cell(s). | |
| Phase 1 Retarget | Checksum: 18cae6d6f | |
| Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6427 ; free virtual = 11486 | |
| INFO: [Opt 31-389] Phase Retarget created 557 cells and removed 1403 cells | |
| INFO: [Opt 31-1021] In phase Retarget, 83 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. | |
| Phase 2 Constant propagation | |
| INFO: [Opt 31-138] Pushed 10 inverter(s) to 10 load pin(s). | |
| Phase 2 Constant propagation | Checksum: 19696cb29 | |
| Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6426 ; free virtual = 11485 | |
| INFO: [Opt 31-389] Phase Constant propagation created 736 cells and removed 3636 cells | |
| INFO: [Opt 31-1021] In phase Constant propagation, 353 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. | |
| Phase 3 Sweep | |
| Phase 3 Sweep | Checksum: e01cbfa3 | |
| Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6426 ; free virtual = 11485 | |
| INFO: [Opt 31-389] Phase Sweep created 6 cells and removed 15234 cells | |
| INFO: [Opt 31-1021] In phase Sweep, 1231 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. | |
| Phase 4 BUFG optimization | |
| INFO: [Opt 31-274] Optimized connectivity to 2 cascaded buffer cells | |
| Phase 4 BUFG optimization | Checksum: 11ea6a120 | |
| Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6428 ; free virtual = 11487 | |
| INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 2 cells. | |
| Phase 5 Shift Register Optimization | |
| INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |
| Phase 5 Shift Register Optimization | Checksum: 11ea6a120 | |
| Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6427 ; free virtual = 11487 | |
| INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |
| Phase 6 Post Processing Netlist | |
| Phase 6 Post Processing Netlist | Checksum: 11c49a1af | |
| Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6428 ; free virtual = 11487 | |
| INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |
| INFO: [Opt 31-1021] In phase Post Processing Netlist, 198 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. | |
| Opt_design Change Summary | |
| ========================= | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| | Retarget | 557 | 1403 | 83 | | |
| | Constant propagation | 736 | 3636 | 353 | | |
| | Sweep | 6 | 15234 | 1231 | | |
| | BUFG optimization | 0 | 2 | 0 | | |
| | Shift Register Optimization | 0 | 0 | 0 | | |
| | Post Processing Netlist | 0 | 0 | 198 | | |
| ------------------------------------------------------------------------------------------------------------------------- | |
| Starting Connectivity Check Task | |
| Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 4016.199 ; gain = 0.000 ; free physical = 6428 ; free virtual = 11487 | |
| Ending Logic Optimization Task | Checksum: 115ec4588 | |
| Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 4016.199 ; gain = 35.672 ; free physical = 6429 ; free virtual = 11488 | |
| Starting Power Optimization Task | |
| INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |
| INFO: [Pwropt 34-9] Applying IDT optimizations ... | |
| INFO: [Pwropt 34-10] Applying ODC optimizations ... | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.046 | TNS=0.000 | | |
| Running Vector-less Activity Propagation... | |
| Finished Running Vector-less Activity Propagation | |
| Starting PowerOpt Patch Enables Task | |
| INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 63 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. | |
| INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports | |
| Number of BRAM Ports augmented: 4 newly gated: 0 Total Ports: 126 | |
| Ending PowerOpt Patch Enables Task | Checksum: 15cbf5595 | |
| Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.68 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5523 ; free virtual = 10717 | |
| Ending Power Optimization Task | Checksum: 15cbf5595 | |
| Time (s): cpu = 00:01:03 ; elapsed = 00:00:37 . Memory (MB): peak = 5552.551 ; gain = 1536.352 ; free physical = 5638 ; free virtual = 10832 | |
| Starting Final Cleanup Task | |
| Ending Final Cleanup Task | Checksum: 15cbf5595 | |
| Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5638 ; free virtual = 10832 | |
| Starting Netlist Obfuscation Task | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5638 ; free virtual = 10832 | |
| Ending Netlist Obfuscation Task | Checksum: 1033d72f5 | |
| Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5638 ; free virtual = 10832 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 227 Infos, 173 Warnings, 3 Critical Warnings and 0 Errors encountered. | |
| opt_design completed successfully | |
| opt_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:12 . Memory (MB): peak = 5552.551 ; gain = 1683.973 ; free physical = 5642 ; free virtual = 10836 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5642 ; free virtual = 10837 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.06 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5630 ; free virtual = 10832 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_opt.dcp' has been generated. | |
| write_checkpoint: Time (s): cpu = 00:00:26 ; elapsed = 00:00:18 . Memory (MB): peak = 5552.551 ; gain = 0.000 ; free physical = 5615 ; free virtual = 10841 | |
| INFO: [runtcl-4] Executing : report_drc -file base_wrapper_drc_opted.rpt -pb base_wrapper_drc_opted.pb -rpx base_wrapper_drc_opted.rpx | |
| Command: report_drc -file base_wrapper_drc_opted.rpt -pb base_wrapper_drc_opted.pb -rpx base_wrapper_drc_opted.rpx | |
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_drc_opted.rpt. | |
| report_drc completed successfully | |
| report_drc: Time (s): cpu = 00:00:16 ; elapsed = 00:00:08 . Memory (MB): peak = 5576.562 ; gain = 24.012 ; free physical = 5605 ; free virtual = 10832 | |
| Command: place_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Running DRC as a precondition to command place_design | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Placer Task | |
| INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs | |
| Phase 1 Placer Initialization | |
| Phase 1.1 Placer Initialization Netlist Sorting | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5602 ; free virtual = 10829 | |
| Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 713880a4 | |
| Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5602 ; free virtual = 10829 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5601 ; free virtual = 10829 | |
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d52ffc14 | |
| Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5414 ; free virtual = 10646 | |
| Phase 1.3 Build Placer Netlist Model | |
| Phase 1.3 Build Placer Netlist Model | Checksum: 13b983a36 | |
| Time (s): cpu = 00:00:50 ; elapsed = 00:00:29 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5237 ; free virtual = 10470 | |
| Phase 1.4 Constrain Clocks/Macros | |
| Phase 1.4 Constrain Clocks/Macros | Checksum: 13b983a36 | |
| Time (s): cpu = 00:00:51 ; elapsed = 00:00:29 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5236 ; free virtual = 10469 | |
| Phase 1 Placer Initialization | Checksum: 13b983a36 | |
| Time (s): cpu = 00:00:51 ; elapsed = 00:00:30 . Memory (MB): peak = 5576.562 ; gain = 0.000 ; free physical = 5235 ; free virtual = 10468 | |
| Phase 2 Global Placement | |
| Phase 2.1 Floorplanning | |
| Phase 2.1 Floorplanning | Checksum: 16d577517 | |
| Time (s): cpu = 00:01:55 ; elapsed = 00:00:58 . Memory (MB): peak = 5577.566 ; gain = 1.004 ; free physical = 5141 ; free virtual = 10375 | |
| Phase 2.2 Global Placement Core | |
| Phase 2.2.1 Physical Synthesis In Placer | |
| INFO: [Physopt 32-76] Pass 1. Identified 1 candidate net for fanout optimization. | |
| INFO: [Physopt 32-81] Processed net base_i/proc_sys_reset_1/U0/peripheral_aresetn[0]. Replicated 2 times. | |
| INFO: [Physopt 32-232] Optimized 1 net. Created 2 new instances. | |
| INFO: [Physopt 32-775] End 1 Pass. Optimized 1 net or cell. Created 2 new cells, deleted 0 existing cell and moved 0 existing cell | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5113 ; free virtual = 10348 | |
| INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. | |
| INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell | |
| INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design | |
| INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell | |
| INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design | |
| INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell | |
| INFO: [Physopt 32-949] No candidate nets found for HD net replication | |
| INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5116 ; free virtual = 10351 | |
| Summary of Physical Synthesis Optimizations | |
| ============================================ | |
| ---------------------------------------------------------------------------------------------------------------------------------------- | |
| | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | | |
| ---------------------------------------------------------------------------------------------------------------------------------------- | |
| | Very High Fanout | 2 | 0 | 1 | 0 | 1 | 00:00:01 | | |
| | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | |
| | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | |
| | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | |
| | HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | |
| | Total | 2 | 0 | 1 | 0 | 5 | 00:00:01 | | |
| ---------------------------------------------------------------------------------------------------------------------------------------- | |
| Phase 2.2.1 Physical Synthesis In Placer | Checksum: 19da0665d | |
| Time (s): cpu = 00:03:30 ; elapsed = 00:02:03 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5111 ; free virtual = 10347 | |
| Phase 2.2 Global Placement Core | Checksum: 119af40d2 | |
| Time (s): cpu = 00:03:44 ; elapsed = 00:02:09 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5091 ; free virtual = 10327 | |
| Phase 2 Global Placement | Checksum: 119af40d2 | |
| Time (s): cpu = 00:03:44 ; elapsed = 00:02:09 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5146 ; free virtual = 10382 | |
| Phase 3 Detail Placement | |
| Phase 3.1 Commit Multi Column Macros | |
| Phase 3.1 Commit Multi Column Macros | Checksum: 156ab4023 | |
| Time (s): cpu = 00:03:49 ; elapsed = 00:02:12 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5144 ; free virtual = 10380 | |
| Phase 3.2 Commit Most Macros & LUTRAMs | |
| Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 152f862d3 | |
| Time (s): cpu = 00:03:57 ; elapsed = 00:02:17 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5135 ; free virtual = 10371 | |
| Phase 3.3 Area Swap Optimization | |
| Phase 3.3 Area Swap Optimization | Checksum: 19daca75a | |
| Time (s): cpu = 00:03:58 ; elapsed = 00:02:18 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5134 ; free virtual = 10370 | |
| Phase 3.4 Small Shape Clustering | |
| Phase 3.4 Small Shape Clustering | Checksum: 180658a10 | |
| Time (s): cpu = 00:04:07 ; elapsed = 00:02:26 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5038 ; free virtual = 10274 | |
| Phase 3.5 Flow Legalize Slice Clusters | |
| Phase 3.5 Flow Legalize Slice Clusters | Checksum: 1b305f551 | |
| Time (s): cpu = 00:04:07 ; elapsed = 00:02:26 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5044 ; free virtual = 10280 | |
| Phase 3.6 Slice Area Swap | |
| Phase 3.6 Slice Area Swap | Checksum: 1b94caba1 | |
| Time (s): cpu = 00:04:14 ; elapsed = 00:02:33 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 4990 ; free virtual = 10226 | |
| Phase 3.7 Commit Slice Clusters | |
| Phase 3.7 Commit Slice Clusters | Checksum: 1e2c9f9a4 | |
| Time (s): cpu = 00:04:35 ; elapsed = 00:02:39 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 4972 ; free virtual = 10208 | |
| Phase 3.8 Re-assign LUT pins | |
| Phase 3.8 Re-assign LUT pins | Checksum: 186f26bc8 | |
| Time (s): cpu = 00:04:41 ; elapsed = 00:02:45 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 4981 ; free virtual = 10217 | |
| Phase 3.9 Pipeline Register Optimization | |
| Phase 3.9 Pipeline Register Optimization | Checksum: 17a17d332 | |
| Time (s): cpu = 00:04:42 ; elapsed = 00:02:46 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5011 ; free virtual = 10247 | |
| Phase 3 Detail Placement | Checksum: 17a17d332 | |
| Time (s): cpu = 00:04:42 ; elapsed = 00:02:46 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5012 ; free virtual = 10248 | |
| Phase 4 Post Placement Optimization and Clean-Up | |
| Phase 4.1 Post Commit Optimization | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Phase 4.1.1 Post Placement Optimization | |
| Post Placement Optimization Initialization | Checksum: 20509e4d7 | |
| Phase 4.1.1.1 BUFG Insertion | |
| INFO: [Place 46-33] Processed net base_i/proc_sys_reset_0/U0/peripheral_aresetn[0], BUFG insertion was skipped due to placement/routing conflicts. | |
| INFO: [Place 46-35] Processed net base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst/SYS_INST/LRST_INST/XPM_RST_INST/syncstages_ff[3], inserted BUFG to drive 2390 loads. | |
| INFO: [Place 46-33] Processed net base_i/proc_sys_reset_0/U0/interconnect_aresetn[0], BUFG insertion was skipped due to placement/routing conflicts. | |
| INFO: [Place 46-35] Processed net base_i/video/phy/vid_phy_controller/inst/xpm_array_single_DRU_CTRL_in_sync_inst/syncstages_ff[2][1], inserted BUFG to drive 1968 loads. | |
| INFO: [Place 46-35] Processed net base_i/video/hdmi_out/frontend/inst/v_tc/U0/U_VIDEO_CTRL/resetn_out, inserted BUFG to drive 1166 loads. | |
| INFO: [Place 46-45] Replicated bufg driver base_i/video/hdmi_out/frontend/inst/v_tc/U0/U_VIDEO_CTRL/AXI4_LITE_INTERFACE.soft_resetn_reg_bufg_rep | |
| INFO: [Place 46-56] BUFG insertion identified 5 candidate nets. Inserted BUFG: 3, Replicated BUFG Driver: 1, Skipped due to Placement/Routing Conflicts: 2, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0. | |
| Phase 4.1.1.1 BUFG Insertion | Checksum: 200a865b4 | |
| Time (s): cpu = 00:05:26 ; elapsed = 00:03:06 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5053 ; free virtual = 10289 | |
| INFO: [Place 30-746] Post Placement Timing Summary WNS=0.602. For the most accurate timing information please run report_timing. | |
| Phase 4.1.1 Post Placement Optimization | Checksum: 209e5a90e | |
| Time (s): cpu = 00:05:27 ; elapsed = 00:03:07 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5055 ; free virtual = 10291 | |
| Phase 4.1 Post Commit Optimization | Checksum: 209e5a90e | |
| Time (s): cpu = 00:05:27 ; elapsed = 00:03:07 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5055 ; free virtual = 10291 | |
| Phase 4.2 Post Placement Cleanup | |
| Phase 4.2 Post Placement Cleanup | Checksum: 209e5a90e | |
| Time (s): cpu = 00:05:28 ; elapsed = 00:03:08 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5069 ; free virtual = 10305 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5066 ; free virtual = 10302 | |
| Phase 4.3 Placer Reporting | |
| Phase 4.3 Placer Reporting | Checksum: 2e396c671 | |
| Time (s): cpu = 00:05:34 ; elapsed = 00:03:14 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5072 ; free virtual = 10309 | |
| Phase 4.4 Final Placement Cleanup | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5072 ; free virtual = 10308 | |
| Phase 4.4 Final Placement Cleanup | Checksum: 2abe0e50e | |
| Time (s): cpu = 00:05:35 ; elapsed = 00:03:15 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5072 ; free virtual = 10308 | |
| Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2abe0e50e | |
| Time (s): cpu = 00:05:35 ; elapsed = 00:03:15 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5072 ; free virtual = 10308 | |
| Ending Placer Task | Checksum: 209936492 | |
| Time (s): cpu = 00:05:35 ; elapsed = 00:03:15 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5072 ; free virtual = 10308 | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 264 Infos, 173 Warnings, 9 Critical Warnings and 0 Errors encountered. | |
| place_design completed successfully | |
| place_design: Time (s): cpu = 00:05:42 ; elapsed = 00:03:19 . Memory (MB): peak = 5585.570 ; gain = 9.008 ; free physical = 5226 ; free virtual = 10462 | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5226 ; free virtual = 10463 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5017 ; free virtual = 10418 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_placed.dcp' has been generated. | |
| write_checkpoint: Time (s): cpu = 00:00:31 ; elapsed = 00:00:19 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5169 ; free virtual = 10455 | |
| INFO: [runtcl-4] Executing : report_io -file base_wrapper_io_placed.rpt | |
| report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.26 . Memory (MB): peak = 5585.570 ; gain = 0.000 ; free physical = 5140 ; free virtual = 10426 | |
| INFO: [runtcl-4] Executing : report_utilization -file base_wrapper_utilization_placed.rpt -pb base_wrapper_utilization_placed.pb | |
| report_utilization: Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 5601.578 ; gain = 16.008 ; free physical = 5162 ; free virtual = 10448 | |
| INFO: [runtcl-4] Executing : report_control_sets -verbose -file base_wrapper_control_sets_placed.rpt | |
| report_control_sets: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 5160 ; free virtual = 10450 | |
| Command: route_design | |
| Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev' | |
| INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev' | |
| Running DRC as a precondition to command route_design | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod0/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO0_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register base_i/iop_pmod1/spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST. It has the property IOB=TRUE, but it is not driving or driven by any IO element. | |
| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 6 Warnings | |
| INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
| Starting Routing Task | |
| INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs | |
| Checksum: PlaceDB: 71d0719c ConstDB: 0 ShapeSum: be11d593 RouteDB: d9b11d63 | |
| Phase 1 Build RT Design | |
| Phase 1 Build RT Design | Checksum: 18a4fb03a | |
| Time (s): cpu = 00:01:02 ; elapsed = 00:00:39 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4878 ; free virtual = 10174 | |
| Post Restoration Checksum: NetGraph: f35f6b00 NumContArr: e84a191d Constraints: a87588b5 Timing: 0 | |
| Phase 2 Router Initialization | |
| Phase 2.1 Create Timer | |
| Phase 2.1 Create Timer | Checksum: 2841f0cd2 | |
| Time (s): cpu = 00:01:03 ; elapsed = 00:00:40 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4844 ; free virtual = 10141 | |
| Phase 2.2 Fix Topology Constraints | |
| Phase 2.2 Fix Topology Constraints | Checksum: 2841f0cd2 | |
| Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4805 ; free virtual = 10101 | |
| Phase 2.3 Pre Route Cleanup | |
| Phase 2.3 Pre Route Cleanup | Checksum: 2841f0cd2 | |
| Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4805 ; free virtual = 10101 | |
| Phase 2.4 Global Clock Net Routing | |
| Number of Nodes with overlaps = 0 | |
| Phase 2.4 Global Clock Net Routing | Checksum: 16f6fc0d5 | |
| Time (s): cpu = 00:01:08 ; elapsed = 00:00:45 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4783 ; free virtual = 10080 | |
| Phase 2.5 Update Timing | |
| Phase 2.5 Update Timing | Checksum: 2a8f604de | |
| Time (s): cpu = 00:01:52 ; elapsed = 00:01:02 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4708 ; free virtual = 10005 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.766 | TNS=0.000 | WHS=-0.502 | THS=-131.120| | |
| Phase 2.6 Update Timing for Bus Skew | |
| Phase 2.6.1 Update Timing | |
| Phase 2.6.1 Update Timing | Checksum: 2077e17f4 | |
| Time (s): cpu = 00:02:42 ; elapsed = 00:01:20 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4698 ; free virtual = 9995 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.766 | TNS=0.000 | WHS=N/A | THS=N/A | | |
| Phase 2.6 Update Timing for Bus Skew | Checksum: 1b2aa13e0 | |
| Time (s): cpu = 00:02:42 ; elapsed = 00:01:20 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4694 ; free virtual = 9992 | |
| Phase 2 Router Initialization | Checksum: 2164b679d | |
| Time (s): cpu = 00:02:42 ; elapsed = 00:01:20 . Memory (MB): peak = 5601.578 ; gain = 0.000 ; free physical = 4694 ; free virtual = 9992 | |
| Router Utilization Summary | |
| Global Vertical Routing Utilization = 0.00505442 % | |
| Global Horizontal Routing Utilization = 0.00576326 % | |
| Routable Net Status* | |
| *Does not include unroutable nets such as driverless and loadless. | |
| Run report_route_status for detailed report. | |
| Number of Failed Nets = 105713 | |
| (Failed Nets is the sum of unrouted and partially routed nets) | |
| Number of Unrouted Nets = 85260 | |
| Number of Partially Routed Nets = 20453 | |
| Number of Node Overlaps = 0 | |
| Phase 3 Initial Routing | |
| Phase 3 Initial Routing | Checksum: 213efcb05 | |
| Time (s): cpu = 00:03:10 ; elapsed = 00:01:32 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4661 ; free virtual = 9959 | |
| Phase 4 Rip-up And Reroute | |
| Phase 4.1 Global Iteration 0 | |
| Number of Nodes with overlaps = 23076 | |
| Number of Nodes with overlaps = 2212 | |
| Number of Nodes with overlaps = 270 | |
| Number of Nodes with overlaps = 29 | |
| Number of Nodes with overlaps = 6 | |
| Number of Nodes with overlaps = 3 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 0 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.258 | TNS=0.000 | WHS=-0.521 | THS=-1.709 | | |
| Phase 4.1 Global Iteration 0 | Checksum: 236a6e78d | |
| Time (s): cpu = 00:05:41 ; elapsed = 00:02:53 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4654 ; free virtual = 9951 | |
| Phase 4.2 Global Iteration 1 | |
| Number of Nodes with overlaps = 11 | |
| Number of Nodes with overlaps = 0 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.258 | TNS=0.000 | WHS=N/A | THS=N/A | | |
| Phase 4.2 Global Iteration 1 | Checksum: 27e38473e | |
| Time (s): cpu = 00:05:49 ; elapsed = 00:02:57 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4643 ; free virtual = 9941 | |
| Phase 4.3 Global Iteration 2 | |
| Number of Nodes with overlaps = 43 | |
| Number of Nodes with overlaps = 6 | |
| Number of Nodes with overlaps = 1 | |
| Number of Nodes with overlaps = 0 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.376 | TNS=0.000 | WHS=N/A | THS=N/A | | |
| Phase 4.3 Global Iteration 2 | Checksum: 31f42c86e | |
| Time (s): cpu = 00:05:55 ; elapsed = 00:03:03 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4650 ; free virtual = 9948 | |
| Phase 4 Rip-up And Reroute | Checksum: 31f42c86e | |
| Time (s): cpu = 00:05:56 ; elapsed = 00:03:04 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4650 ; free virtual = 9948 | |
| Phase 5 Delay and Skew Optimization | |
| Phase 5.1 Delay CleanUp | |
| Phase 5.1 Delay CleanUp | Checksum: 32053b9b9 | |
| Time (s): cpu = 00:05:56 ; elapsed = 00:03:04 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4655 ; free virtual = 9952 | |
| Phase 5.2 Clock Skew Optimization | |
| Phase 5.2 Clock Skew Optimization | Checksum: 32053b9b9 | |
| Time (s): cpu = 00:05:56 ; elapsed = 00:03:04 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4655 ; free virtual = 9952 | |
| Phase 5 Delay and Skew Optimization | Checksum: 32053b9b9 | |
| Time (s): cpu = 00:05:56 ; elapsed = 00:03:04 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4655 ; free virtual = 9953 | |
| Phase 6 Post Hold Fix | |
| Phase 6.1 Hold Fix Iter | |
| Phase 6.1.1 Update Timing | |
| Phase 6.1.1 Update Timing | Checksum: 2cd11525e | |
| Time (s): cpu = 00:06:14 ; elapsed = 00:03:11 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4659 ; free virtual = 9957 | |
| INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.376 | TNS=0.000 | WHS=0.010 | THS=0.000 | | |
| Phase 6.1 Hold Fix Iter | Checksum: 2781f8022 | |
| Time (s): cpu = 00:06:14 ; elapsed = 00:03:12 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4659 ; free virtual = 9957 | |
| Phase 6 Post Hold Fix | Checksum: 2781f8022 | |
| Time (s): cpu = 00:06:15 ; elapsed = 00:03:12 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4659 ; free virtual = 9957 | |
| Phase 7 Route finalize | |
| Router Utilization Summary | |
| Global Vertical Routing Utilization = 5.92837 % | |
| Global Horizontal Routing Utilization = 6.93058 % | |
| Routable Net Status* | |
| *Does not include unroutable nets such as driverless and loadless. | |
| Run report_route_status for detailed report. | |
| Number of Failed Nets = 0 | |
| (Failed Nets is the sum of unrouted and partially routed nets) | |
| Number of Unrouted Nets = 0 | |
| Number of Partially Routed Nets = 0 | |
| Number of Node Overlaps = 0 | |
| Phase 7 Route finalize | Checksum: 28d34d1c2 | |
| Time (s): cpu = 00:06:16 ; elapsed = 00:03:13 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4656 ; free virtual = 9954 | |
| Phase 8 Verifying routed nets | |
| Verification completed successfully | |
| Phase 8 Verifying routed nets | Checksum: 28d34d1c2 | |
| Time (s): cpu = 00:06:16 ; elapsed = 00:03:13 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4654 ; free virtual = 9952 | |
| Phase 9 Depositing Routes | |
| Phase 9 Depositing Routes | Checksum: 28d34d1c2 | |
| Time (s): cpu = 00:06:23 ; elapsed = 00:03:20 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4659 ; free virtual = 9957 | |
| Phase 10 Post Router Timing | |
| INFO: [Route 35-57] Estimated Timing Summary | WNS=0.376 | TNS=0.000 | WHS=0.010 | THS=0.000 | | |
| INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. | |
| Phase 10 Post Router Timing | Checksum: 28d34d1c2 | |
| Time (s): cpu = 00:06:23 ; elapsed = 00:03:20 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4667 ; free virtual = 9965 | |
| INFO: [Route 35-16] Router Completed Successfully | |
| Time (s): cpu = 00:06:23 ; elapsed = 00:03:20 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4759 ; free virtual = 10057 | |
| Routing Is Done. | |
| INFO: [Common 17-83] Releasing license: Implementation | |
| 284 Infos, 179 Warnings, 9 Critical Warnings and 0 Errors encountered. | |
| route_design completed successfully | |
| route_design: Time (s): cpu = 00:06:33 ; elapsed = 00:03:24 . Memory (MB): peak = 5637.566 ; gain = 35.988 ; free physical = 4759 ; free virtual = 10057 | |
| INFO: [Common 17-600] The following parameters have non-default value. | |
| general.maxThreads | |
| Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 5637.566 ; gain = 0.000 ; free physical = 4759 ; free virtual = 10057 | |
| INFO: [Timing 38-480] Writing timing data to binary archive. | |
| Writing placer database... | |
| Writing XDEF routing. | |
| Writing XDEF routing logical nets. | |
| Writing XDEF routing special nets. | |
| Write XDEF Complete: Time (s): cpu = 00:00:12 ; elapsed = 00:00:04 . Memory (MB): peak = 5637.566 ; gain = 0.000 ; free physical = 4500 ; free virtual = 10007 | |
| INFO: [Common 17-1381] The checkpoint '/home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_routed.dcp' has been generated. | |
| write_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:20 . Memory (MB): peak = 5637.566 ; gain = 0.000 ; free physical = 4689 ; free virtual = 10048 | |
| INFO: [runtcl-4] Executing : report_drc -file base_wrapper_drc_routed.rpt -pb base_wrapper_drc_routed.pb -rpx base_wrapper_drc_routed.rpx | |
| Command: report_drc -file base_wrapper_drc_routed.rpt -pb base_wrapper_drc_routed.pb -rpx base_wrapper_drc_routed.rpx | |
| INFO: [IP_Flow 19-1839] IP Catalog is up to date. | |
| INFO: [DRC 23-27] Running DRC with 4 threads | |
| INFO: [Coretcl 2-168] The results of DRC are in file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_drc_routed.rpt. | |
| report_drc completed successfully | |
| report_drc: Time (s): cpu = 00:00:28 ; elapsed = 00:00:13 . Memory (MB): peak = 5645.570 ; gain = 8.004 ; free physical = 4643 ; free virtual = 10001 | |
| INFO: [runtcl-4] Executing : report_methodology -file base_wrapper_methodology_drc_routed.rpt -pb base_wrapper_methodology_drc_routed.pb -rpx base_wrapper_methodology_drc_routed.rpx | |
| Command: report_methodology -file base_wrapper_methodology_drc_routed.rpt -pb base_wrapper_methodology_drc_routed.pb -rpx base_wrapper_methodology_drc_routed.rpx | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| INFO: [DRC 23-133] Running Methodology with 4 threads | |
| INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/pcarr/PYNQ/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/base_wrapper_methodology_drc_routed.rpt. | |
| report_methodology completed successfully | |
| report_methodology: Time (s): cpu = 00:01:02 ; elapsed = 00:00:24 . Memory (MB): peak = 5917.816 ; gain = 272.246 ; free physical = 4587 ; free virtual = 9946 | |
| INFO: [runtcl-4] Executing : report_power -file base_wrapper_power_routed.rpt -pb base_wrapper_power_summary_routed.pb -rpx base_wrapper_power_routed.rpx | |
| Command: report_power -file base_wrapper_power_routed.rpt -pb base_wrapper_power_summary_routed.pb -rpx base_wrapper_power_routed.rpx | |
| INFO: [Timing 38-35] Done setting XDC timing constraints. | |
| Running Vector-less Activity Propagation... | |
| Finished Running Vector-less Activity Propagation | |
| WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. | |
| Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. | |
| 297 Infos, 180 Warnings, 9 Critical Warnings and 0 Errors encountered. | |
| report_power completed successfully | |
| report_power: Time (s): cpu = 00:00:43 ; elapsed = 00:00:28 . Memory (MB): peak = 5917.816 ; gain = 0.000 ; free physical = 4448 ; free virtual = 9823 | |
| INFO: [runtcl-4] Executing : report_route_status -file base_wrapper_route_status.rpt -pb base_wrapper_route_status.pb | |
| INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file base_wrapper_timing_summary_routed.rpt -pb base_wrapper_timing_summary_routed.pb -rpx base_wrapper_timing_summary_routed.rpx -warn_on_violation | |
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. | |
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs | |
| WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. | |
| INFO: [runtcl-4] Executing : report_incremental_reuse -file base_wrapper_incremental_reuse_routed.rpt | |
| INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. | |
| INFO: [runtcl-4] Executing : report_clock_utilization -file base_wrapper_clock_utilization_routed.rpt | |
| report_clock_utilization: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 5917.816 ; gain = 0.000 ; free physical = 4385 ; free virtual = 9774 | |
| INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file base_wrapper_bus_skew_routed.rpt -pb base_wrapper_bus_skew_routed.pb -rpx base_wrapper_bus_skew_routed.rpx | |
| INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max. | |
| INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs | |
| INFO: [Memdata 28-208] The XPM instance: <base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <base_i/video/hdmi_out/frontend/inst/v_axi4s_vid_out>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. | |
| INFO: [Memdata 28-208] The XPM instance: <base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s/inst/COUPLER_INST/generate_async_fifo.FIFO_INST/XPM_FIFO_ASYNC_INST/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <base_i/video/hdmi_in/frontend/inst/v_vid_in_axi4s>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-208] The XPM instance: <base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <base_i/video/axi_vdma>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. | |
| INFO: [Memdata 28-208] The XPM instance: <base_i/video/axi_vdma/U0/I_PRMRY_DATAMOVER/GEN_MM2S_FULL.I_MM2S_FULL_WRAPPER/GEN_INCLUDE_MM2S_SF.I_RD_SF/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst> is part of IP: <base_i/video/axi_vdma>. This XPM instance will be excluded from the .mmi because updatemem is prohibited from making changes to an XPM that is part of an IP. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_LINEBUFFER_FLUSH_SOF.GEN_SYNC_FIFO_FLUSH_SOF.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to auto. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/video/axi_vdma/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_SYNC_FIFO.I_LINEBUFFER_FIFO/xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_wdata_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_wc/i_waddr_channel/i_input_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_top/i_rc/i_rdata_channel/i_output_buffer/gen_0_xpm_fifo.i_fifo/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst block. | |
| INFO: [Memdata 28-167] Found XPM memory block base_i/shutdown_LPD/U0/i_top/gen_axi4mm.i_axi4mm_ |
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