disassembly

build.elf:     file format elf32-littlearm


Disassembly of section .isr_vector:

00000000 <vectors>:
   0:	20005000 	andcs	r5, r0, r0
   4:	000000b7 	strheq	r0, [r0], -r7
   8:	000000b1 	strheq	r0, [r0], -r1
   c:	000000b1 	strheq	r0, [r0], -r1
  10:	000000b1 	strheq	r0, [r0], -r1
  14:	000000b1 	strheq	r0, [r0], -r1
  18:	000000b1 	strheq	r0, [r0], -r1
  1c:	000000b1 	strheq	r0, [r0], -r1
  20:	000000b1 	strheq	r0, [r0], -r1
  24:	000000b1 	strheq	r0, [r0], -r1
  28:	000000b1 	strheq	r0, [r0], -r1
  2c:	000000b1 	strheq	r0, [r0], -r1
  30:	000000b1 	strheq	r0, [r0], -r1
  34:	000000b1 	strheq	r0, [r0], -r1
  38:	000000b1 	strheq	r0, [r0], -r1
  3c:	000000b1 	strheq	r0, [r0], -r1

Disassembly of section .text:

00000040 <main>:
  40:	b480      	push	{r7}
  42:	b083      	sub	sp, #12
  44:	af00      	add	r7, sp, #0
  46:	4b16      	ldr	r3, [pc, #88]	; (a0 <main+0x60>)
  48:	681b      	ldr	r3, [r3, #0]
  4a:	f103 53a0 	add.w	r3, r3, #335544320	; 0x14000000
  4e:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
  52:	009b      	lsls	r3, r3, #2
  54:	461a      	mov	r2, r3
  56:	2301      	movs	r3, #1
  58:	6013      	str	r3, [r2, #0]
  5a:	4a12      	ldr	r2, [pc, #72]	; (a4 <main+0x64>)
  5c:	4b10      	ldr	r3, [pc, #64]	; (a0 <main+0x60>)
  5e:	681b      	ldr	r3, [r3, #0]
  60:	2101      	movs	r1, #1
  62:	fa01 f303 	lsl.w	r3, r1, r3
  66:	6013      	str	r3, [r2, #0]
  68:	2300      	movs	r3, #0
  6a:	607b      	str	r3, [r7, #4]
  6c:	e002      	b.n	74 <main+0x34>
  6e:	687b      	ldr	r3, [r7, #4]
  70:	3301      	adds	r3, #1
  72:	607b      	str	r3, [r7, #4]
  74:	687b      	ldr	r3, [r7, #4]
  76:	4a0c      	ldr	r2, [pc, #48]	; (a8 <main+0x68>)
  78:	4293      	cmp	r3, r2
  7a:	ddf8      	ble.n	6e <main+0x2e>
  7c:	4a0b      	ldr	r2, [pc, #44]	; (ac <main+0x6c>)
  7e:	4b08      	ldr	r3, [pc, #32]	; (a0 <main+0x60>)
  80:	681b      	ldr	r3, [r3, #0]
  82:	2101      	movs	r1, #1
  84:	fa01 f303 	lsl.w	r3, r1, r3
  88:	6013      	str	r3, [r2, #0]
  8a:	2300      	movs	r3, #0
  8c:	603b      	str	r3, [r7, #0]
  8e:	e002      	b.n	96 <main+0x56>
  90:	683b      	ldr	r3, [r7, #0]
  92:	3301      	adds	r3, #1
  94:	603b      	str	r3, [r7, #0]
  96:	683b      	ldr	r3, [r7, #0]
  98:	4a03      	ldr	r2, [pc, #12]	; (a8 <main+0x68>)
  9a:	4293      	cmp	r3, r2
  9c:	ddf8      	ble.n	90 <main+0x50>
  9e:	e7dc      	b.n	5a <main+0x1a>
  a0:	20000000 	andcs	r0, r0, r0
  a4:	50000508 	andpl	r0, r0, r8, lsl #10
  a8:	000f423f 	andeq	r4, pc, pc, lsr r2	; <UNPREDICTABLE>
  ac:	5000050c 	andpl	r0, r0, ip, lsl #10

000000b0 <dummy_fn>:
  b0:	b480      	push	{r7}
  b2:	af00      	add	r7, sp, #0
  b4:	e7fe      	b.n	b4 <dummy_fn+0x4>

000000b6 <c_startup>:
  b6:	b580      	push	{r7, lr}
  b8:	b082      	sub	sp, #8
  ba:	af00      	add	r7, sp, #0
  bc:	4b11      	ldr	r3, [pc, #68]	; (104 <c_startup+0x4e>)
  be:	607b      	str	r3, [r7, #4]
  c0:	4b11      	ldr	r3, [pc, #68]	; (108 <c_startup+0x52>)
  c2:	603b      	str	r3, [r7, #0]
  c4:	e007      	b.n	d6 <c_startup+0x20>
  c6:	683b      	ldr	r3, [r7, #0]
  c8:	1d1a      	adds	r2, r3, #4
  ca:	603a      	str	r2, [r7, #0]
  cc:	687a      	ldr	r2, [r7, #4]
  ce:	1d11      	adds	r1, r2, #4
  d0:	6079      	str	r1, [r7, #4]
  d2:	6812      	ldr	r2, [r2, #0]
  d4:	601a      	str	r2, [r3, #0]
  d6:	683b      	ldr	r3, [r7, #0]
  d8:	4a0c      	ldr	r2, [pc, #48]	; (10c <c_startup+0x56>)
  da:	4293      	cmp	r3, r2
  dc:	d3f3      	bcc.n	c6 <c_startup+0x10>
  de:	4b0c      	ldr	r3, [pc, #48]	; (110 <c_startup+0x5a>)
  e0:	607b      	str	r3, [r7, #4]
  e2:	e004      	b.n	ee <c_startup+0x38>
  e4:	687b      	ldr	r3, [r7, #4]
  e6:	1d1a      	adds	r2, r3, #4
  e8:	607a      	str	r2, [r7, #4]
  ea:	2200      	movs	r2, #0
  ec:	601a      	str	r2, [r3, #0]
  ee:	687b      	ldr	r3, [r7, #4]
  f0:	4a08      	ldr	r2, [pc, #32]	; (114 <c_startup+0x5e>)
  f2:	4293      	cmp	r3, r2
  f4:	d3f6      	bcc.n	e4 <c_startup+0x2e>
  f6:	f7ff ffa3 	bl	40 <main>
  fa:	bf00      	nop
  fc:	3708      	adds	r7, #8
  fe:	46bd      	mov	sp, r7
 100:	bd80      	pop	{r7, pc}
 102:	bf00      	nop
 104:	00000118 	andeq	r0, r0, r8, lsl r1
 108:	20000000 	andcs	r0, r0, r0
 10c:	20000004 	andcs	r0, r0, r4
 110:	20000004 	andcs	r0, r0, r4
 114:	20000004 	andcs	r0, r0, r4

Disassembly of section .data:

20000000 <LED>:
20000000:	00000011 	andeq	r0, r0, r1, lsl r0