Creating SHM waveforms with irun

shm_waveforms.md

To run a verilog simulation using irun and create a shm waveform file,

initial begin
  $shm_open("waves.shm"); $shm_probe("AS");
end

run with irun -access +r testcase.sv

Or create this tcl file:

shm.tcl

database -open waves -shm
probe -create your_top_level -depth all -all -shm -database waves
run 
exit

run with :

irun -access +r testcase.sv -input shm.tcl

Found some shm_probe() arguments somewhere on the web, might be useful here:
Shm_probe("");
A: all nodes, including inputs, outputs and inouts, of the specified scope 
S: inputs, outputs and inouts of the specified scope, and in all instantiations below it, except inside library cells. 
C: inputs, outputs and inouts of the specifed scope, and in all instantiations  below it, including those inside library cells. 
AS: all nodes, including inputs, outputs and inouts, of the specified scope, and in all instantiations below it, except inside library cells. 
AC: all nodes, including inputs outputs and inouts, in the specified scope and in all instantiations below it, even inside library cells. 

To add Memories to the shm_probe command add 'M' to the end of the option ie.

$shm_probe("ASM");

how can we enable different hierarchy ? can we pass the hierarchy from valueplusargs? whats the type of hierarchy expression,

if we pass the hierarchy as string I see error as E,SHMSTR () Illegal string argument.

@shanthab2 For controlling hierarchy using the tcl file is best. Cadence tools have this example:
I can not get the shm_probe command to accept a hierarchy that is in the form "Testharness.dut_1"

//shm probe
integer i, j;

module test_2;

initial begin
  $shm_open ("comp_units");
  $shm_probe ("ASCTF", $unit::i, $unit::j); end
initial begin
// ...
#10 $finish;
end
 endmodule

Hi @morganp , Thanks for the info,
Do we have any option to enable power dump also wit $shm_probe like M for memories ?

Hi @morganp how can i dump testcase signals rather than top.tb in UVM?