Ram.fir

  module NttRam : 
    input clock : Clock
    input reset : Reset
    output io : {port : {flip req : {valid : UInt<1>, bits : {addr : UInt<8>, write : {valid : UInt<1>, bits : SInt<13>[4]}}}, resp : {valid : UInt<1>, bits : SInt<13>[4]}}[2]}
    
    node _T = asUInt(io.port[0].resp.bits[0]) @[Ram.scala 54:62]
    node _T_1 = asUInt(io.port[0].resp.bits[1]) @[Ram.scala 54:62]
    node _T_2 = asUInt(io.port[0].resp.bits[2]) @[Ram.scala 54:62]
    node _T_3 = asUInt(io.port[0].resp.bits[3]) @[Ram.scala 54:62]
    node _T_4 = cat(_T_1, _T) @[Ram.scala 54:62]
    node _T_5 = cat(_T_3, _T_2) @[Ram.scala 54:62]
    node _T_6 = cat(_T_5, _T_4) @[Ram.scala 54:62]
    smem NttRam : UInt<52>[256], undefined @[Ram.scala 54:32]
    reg _T_7 : UInt<1>, clock @[Ram.scala 57:35]
    _T_7 <= io.port[0].req.valid @[Ram.scala 57:35]
    io.port[0].resp.valid <= _T_7 @[Ram.scala 57:25]
    wire _T_8 : UInt @[Ram.scala 58:35]
    _T_8 is invalid @[Ram.scala 58:35]
    when io.port[0].req.valid : @[Ram.scala 58:35]
      _T_8 <= io.port[0].req.bits.addr @[Ram.scala 58:35]
      node _T_9 = or(_T_8, UInt<8>("h00")) @[Ram.scala 58:35]
      node _T_10 = bits(_T_9, 7, 0) @[Ram.scala 58:35]
      read mport _T_11 = NttRam[_T_10], clock @[Ram.scala 58:35]
      skip @[Ram.scala 58:35]
    wire _T_12 : SInt<13>[4] @[Ram.scala 58:92]
    wire _T_13 : UInt<52>
    _T_13 <= _T_11
    node _T_14 = bits(_T_13, 12, 0) @[Ram.scala 58:92]
    node _T_15 = asSInt(_T_14) @[Ram.scala 58:92]
    _T_12[0] <= _T_15 @[Ram.scala 58:92]
    node _T_16 = bits(_T_13, 25, 13) @[Ram.scala 58:92]
    node _T_17 = asSInt(_T_16) @[Ram.scala 58:92]
    _T_12[1] <= _T_17 @[Ram.scala 58:92]
    node _T_18 = bits(_T_13, 38, 26) @[Ram.scala 58:92]
    node _T_19 = asSInt(_T_18) @[Ram.scala 58:92]
    _T_12[2] <= _T_19 @[Ram.scala 58:92]
    node _T_20 = bits(_T_13, 51, 39) @[Ram.scala 58:92]
    node _T_21 = asSInt(_T_20) @[Ram.scala 58:92]
    _T_12[3] <= _T_21 @[Ram.scala 58:92]
    io.port[0].resp.bits[0] <= _T_12[0] @[Ram.scala 58:24]
    io.port[0].resp.bits[1] <= _T_12[1] @[Ram.scala 58:24]
    io.port[0].resp.bits[2] <= _T_12[2] @[Ram.scala 58:24]
    io.port[0].resp.bits[3] <= _T_12[3] @[Ram.scala 58:24]
    io.port[1].resp.valid is invalid @[Ram.scala 60:25]
    io.port[1].resp.bits[0] is invalid @[Ram.scala 61:24]
    io.port[1].resp.bits[1] is invalid @[Ram.scala 61:24]
    io.port[1].resp.bits[2] is invalid @[Ram.scala 61:24]
    io.port[1].resp.bits[3] is invalid @[Ram.scala 61:24]
    when io.port[1].req.bits.write.valid : @[Ram.scala 63:41]
      node _T_22 = asUInt(io.port[1].req.bits.write.bits[0]) @[Ram.scala 64:72]
      node _T_23 = asUInt(io.port[1].req.bits.write.bits[1]) @[Ram.scala 64:72]
      node _T_24 = asUInt(io.port[1].req.bits.write.bits[2]) @[Ram.scala 64:72]
      node _T_25 = asUInt(io.port[1].req.bits.write.bits[3]) @[Ram.scala 64:72]
      node _T_26 = cat(_T_23, _T_22) @[Ram.scala 64:72]
      node _T_27 = cat(_T_25, _T_24) @[Ram.scala 64:72]
      node _T_28 = cat(_T_27, _T_26) @[Ram.scala 64:72]
      write mport _T_29 = NttRam[io.port[1].req.bits.addr], clock
      _T_29 <= _T_28
      skip @[Ram.scala 63:41]