librelane_step_by_step_example.py

###### PDK Setup ######

import ciel
from ciel.source import StaticWebDataSource
from librelane.common import get_opdks_rev, ScopedFile

ciel.enable(
    ciel.get_ciel_home(),
    "sky130",
    get_opdks_rev(),
    data_source=StaticWebDataSource("https://fossi-foundation.github.io/ciel-releases"),
)

##### Configuration #####
from librelane.config import Config

Config.interactive(
    "spm",
    PDK="sky130A",
    CLOCK_PORT="clk",
    CLOCK_NET="clk",
    CLOCK_PERIOD=10,
    PRIMARY_GDSII_STREAMOUT_TOOL="klayout",
)

##### Steps #####
from librelane.steps import Step
from librelane.state import State

initial_state = State()

Synthesis = Step.factory.get("Yosys.Synthesis")
print(Synthesis.get_help_md())

# You can also just give a path to pre-existing file instead
with open("spm.v", "w") as f:
    f.write(
        """
    module spm #(parameter bits=32) (
        input clk,
        input rst,
        input x,
        input[bits-1: 0] a,
        output y
    );
        wire[bits: 0] y_chain;
        assign y_chain[0] = 0;
        assign y = y_chain[bits];

        wire[bits-1:0] a_flip;
        genvar i;
        generate 
            for (i = 0; i < bits; i = i + 1) begin : flip_block
                assign a_flip[i] = a[bits - i - 1];
            end 
        endgenerate

        delayed_serial_adder dsa[bits-1:0](
            .clk(clk),
            .rst(rst),
            .x(x),
            .a(a_flip),
            .y_in(y_chain[bits-1:0]),
            .y_out(y_chain[bits:1])
        );

    endmodule

    module delayed_serial_adder(
        input clk,
        input rst,
        input x,
        input a,
        input y_in,
        output reg y_out
    );
        reg last_carry;
        wire last_carry_next;
        wire y_out_next;

        wire g = x & a;
        assign {last_carry_next, y_out_next} = g + y_in + last_carry;

        always @ (posedge clk or negedge rst) begin
            if (!rst) begin
                last_carry <= 1'b0;
                y_out <= 1'b0;
            end else begin
                last_carry <= last_carry_next;
                y_out <= y_out_next;
            end
        end
    endmodule
    """
    )

synthesis = Synthesis(state_in=initial_state, VERILOG_FILES=["spm.v"])
synthesis.start()

# … add more steps here

# step list:
#   https://librelane.readthedocs.io/en/latest/reference/step_config_vars.html