Verilog modeling of inertial bus changes #verilog

bus_hazards_tolerant_model.rst

Tolerate Glitches on Bus Transitioning between Stable States

This example shows how to use Verilog inertial delay modeling to avoid dynamic hazards on a bus changing from one stable state to another, such as when caused by differences in delays of individual bits.

tb.sv

`timescale 1ns/1ps

module tb;

logic[1:0] a;
logic[1:0] ao;
logic b;

my_cell dut(.a, .b, .ao);

task aa( input logic[1:0] v);
    a = v;
    $display("%0t: a=%b", $realtime, a);
endtask


initial begin
    $timeformat(-9, 3, " ns", 10);

    aa(2'b01);
    #1ns;

    aa(2'b11);
    #1ns;

    aa(2'b10);
    #2ns;

    $display("---");

    aa(2'b00);
    #50ps;

    aa(2'b01);
    #2ns;

    $display("---");

    aa(2'b00);
    #200ps;

    aa(2'b10);
    #2ns;

    $display("---");

    $display("%0t: then", $realtime);
    #1;
    $display("%0t: now", $realtime);

    $stop;
end

always @(b) begin
    $display("%0t: b=%b", $realtime, b);
end

always @(ao) begin
    $display("%0t: ao=%b", $realtime, ao);
end

endmodule

test_cell.v

`timescale 1ns/1ps

module my_cell(a,b,ao);
input [1:0] a;
wire [1:0] a;

output b;
reg b;

output [1:0] ao;
wire [1:0] ao;

reg [1:0] a_inert;

wire oh;
assign oh = (a==2'b01) | (a==2'b10);

specify
    specparam ti = 0.1;
endspecify

always @(a) #ti a_inert = a;

always @(*) begin
    if (oh) b <= a[0];
    else b <= 1'bx;
end

always @(a_inert) begin
    if ((a_inert != 2'b01) && (a_inert != 2'b10)) begin
        $warning("`a` not one-hot coded: %b", a_inert);
    end
end

assign ao = a_inert;

endmodule