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Dell XPS 15 9560 (1.2.5) NVRAM edits
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# Set Intel(R) Speed Shift Technology to Enabled | |
setup_var 0x4BC 0x1 | |
# Set CFG Lock to Disabled | |
setup_var 0x4ED 0x0 | |
# Set Above 4GB MMIO BIOS assignment to Enabled | |
# setup_var 0x79A 0x1 | |
# Set EHCI Hand-off to Disabled | |
# setup_var 0x2 0x0 | |
# Set XHCI Hand-off to Disabled | |
# setup_var 0x1B 0x0 | |
# Set Low Power S0 Idle Capability to Enabled | |
setup_var 0x13 0x1 | |
# Set DVMT Total Gfx Mem to MAX | |
# setup_var 0x796 0x3 | |
# Set Overclocking Lock to Disabled | |
# setup_var 0x59C 0x0 | |
# Set OverClocking Feature to Enabled | |
setup_var 0x65C 0x1 | |
# Set XTU Interface to Enabled | |
setup_var 0x65D 0x1 | |
# Set Core Voltage Offset Prefix to Negative | |
setup_var 0x664 0x1 | |
# Set Core Voltage Offset to -120 mV | |
setup_var 0x662 0x78 | |
# Set Uncore Voltage Offset Prefix to Negative | |
setup_var 0x865 0x1 | |
# Set Uncore Voltage Offset to -100 mV | |
setup_var 0x863 0x64 | |
# Set GT Voltage Offset Prefix to Negative | |
setup_var 0x86D 0x1 | |
# Set GT Voltage Offset to -100 mV | |
setup_var 0x86B 0x64 | |
# Set GT Unsliced Voltage Offset Prefix to Negative | |
setup_var 0x876 0x1 | |
# Set GT Unsliced Voltage Offset to -100 mV | |
setup_var 0x874 0x64 | |
# Set PCI Express Root Port 13 to Disabled | |
setup_var 0x95A 0x0 | |
# DCI killed in recent BIOS version? | |
# chipsec -m chipsec.modules.common.debugenabled reports DCI Debug is disabled even after setting these | |
# Set Debug Interface to Enabled | |
# setup_var 0x59D 0x1 | |
# Set Debug Interface Lock to Disabled | |
# setup_var 0x59E 0x0 | |
# Set Direct Connect Interface to Enabled | |
# setup_var 0x59F 0x1 | |
# Set DCI enable (HDCIEN) to Enabled | |
# setup_var 0x899 0x1 | |
# Set TraceHub Enable Mode to Host Debugger | |
# setup_var 0xEAF 0x2 |
On a sidenote, if anyone ever copy paste the config.
Do not enable "Set Low Power S0 Idle Capability to Enabled", otherwise sleep does not work anymore.
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Unfortunately the bit is reset upon reboot. The only way would be via SPI flash with physical access to the chip using a programmer.