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# perform a fresh install of Ubuntu 17.10
# upgrade the kernel to v4.13.10
mkdir ~/kernel-v4.13.10
cd ~/kernel-v4.13.10
wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.13.10/linux-headers-4.13.10-041310_4.13.10-041310.201710270531_all.deb
wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.13.10/linux-headers-4.13.10-041310-generic_4.13.10-041310.201710270531_amd64.deb
wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.13.10/linux-image-4.13.10-041310-generic_4.13.10-041310.201710270531_amd64.deb
sudo dpkg -i *.deb
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Miliox / GameBoy Bootstrap ROM spiegata
Created August 29, 2016 14:59 — forked from MirkoPani/GameBoy Bootstrap ROM spiegata
GameBoy Bootstrap ROM Commentata
LD SP,$fffe ; $0000 Inizializza Stack- copia $fffe in SP (Stack Pointer)
XOR A ; $0003 Setta a 0 la memoria da $8000-$9FFF (VRAM) (xor tra A e se stesso=tutti 0 essendo bit uguali)
LD HL,$9fff ; $0004 Setta HL- puntatore per pulire la VRAM
Addr_0007:
LD (HL-),A ; $0007 Setta HL a 0 (essendo A tutti bit 0), decrementa HL portandolo a $9ffe
BIT 7,H ; $0008 Bit piu significante di H=$9f= 10011111 ossia 1 - zero flag del registro F viene pulito
JR NZ, Addr_0007 ; $000a jump if not zero to address 0x000C-0x0005=0x0007
questa procedura qui sopra continua in loop scrivendo 0 in $9FFE,$9FFD...fintanto che
il jump viene annullato=condizione 'not zero' vera.
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Miliox / The Technical Interview Cheat Sheet.md
Last active August 29, 2015 14:28 — forked from tsiege/The Technical Interview Cheat Sheet.md
This is my technical interview cheat sheet. Feel free to fork it or do whatever you want with it. PLEASE let me know if there are any errors or if anything crucial is missing. I will add more links soon.

Studying for a Tech Interview Sucks, so Here's a Cheat Sheet to Help

This list is meant to be a both a quick guide and reference for further research into these topics. It's basically a summary of that comp sci course you never took or forgot about, so there's no way it can cover everything in depth. It also will be available as a gist on Github for everyone to edit and add to.

Data Structure Basics

###Array ####Definition:

  • Stores data elements based on an sequential, most commonly 0 based, index.
  • Based on tuples from set theory.
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Miliox / NewClasses
Last active August 29, 2015 14:18 — forked from dotMorten/NewClasses
Windows.ApplicationModel.Activation.FileOpenPickerContinuationEventArgs
Windows.ApplicationModel.Activation.FileSavePickerContinuationEventArgs
Windows.ApplicationModel.Activation.FolderPickerContinuationEventArgs
Windows.ApplicationModel.Activation.IContinuationActivatedEventArgs
Windows.ApplicationModel.Activation.IFileOpenPickerContinuationEventArgs
Windows.ApplicationModel.Activation.IFileSavePickerContinuationEventArgs
Windows.ApplicationModel.Activation.IFolderPickerContinuationEventArgs
Windows.ApplicationModel.Activation.IWebAccountProviderActivatedEventArgs
Windows.ApplicationModel.Activation.IWebAccountProviderContinuationEventArgs
Windows.ApplicationModel.Activation.WebAccountProviderActivatedEventArgs

Latency numbers every programmer should know

L1 cache reference ......................... 0.5 ns
Branch mispredict ............................ 5 ns
L2 cache reference ........................... 7 ns
Mutex lock/unlock ........................... 25 ns
Main memory reference ...................... 100 ns             
Compress 1K bytes with Zippy ............. 3,000 ns  =   3 µs
Send 2K bytes over 1 Gbps network ....... 20,000 ns  =  20 µs
SSD random read ........................ 150,000 ns  = 150 µs

Read 1 MB sequentially from memory ..... 250,000 ns = 250 µs

oclint 0.9 / [stackoverflow]

mkdir build; cd build
scan-build cmake ..

....

oclint-json-compilation-database -v oclint_args \
  "-allow-duplicated-violations -enable-clang-static-analyzer \
  -enable-global-analysis -list-enabled-rules \
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Miliox / latency.txt
Last active August 29, 2015 14:12 — forked from jboner/latency.txt
Latency Comparison Numbers
--------------------------
L1 cache reference 0.5 ns
Branch mispredict 5 ns
L2 cache reference 7 ns 14x L1 cache
Mutex lock/unlock 25 ns
Main memory reference 100 ns 20x L2 cache, 200x L1 cache
Compress 1K bytes with Zippy 3,000 ns
Send 1K bytes over 1 Gbps network 10,000 ns 0.01 ms
Read 4K randomly from SSD* 150,000 ns 0.15 ms