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Forty-Bot/cells_sim.v

Created September 2, 2022 06:08
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cells_sim.v
/* Generated by Yosys 0.19 (git sha1 a45c131b3, gcc 12.1.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2136.1-2420.10" *)
module ICESTORM_LC(I0, I1, I2, I3, CIN, CLK, CEN, SR, LO, O, COUT);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.34-2137.37" *)
input CEN;
wire CEN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.24-2137.27" *)
input CIN;
wire CIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.29-2137.32" *)
input CLK;
wire CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2140.9-2140.13" *)
output COUT;
wire COUT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.8-2137.10" *)
input I0;
wire I0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.12-2137.14" *)
input I1;
wire I1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.16-2137.18" *)
input I2;
wire I2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.20-2137.22" *)
input I3;
wire I3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2138.9-2138.11" *)
output LO;
wire LO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2139.9-2139.10" *)
output O;
wire O;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2137.39-2137.41" *)
input SR;
wire SR;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:3167.1-3502.10" *)
module ICESTORM_RAM(RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0, RCLK, RCLKE, RE, RADDR_10, RADDR_9
, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0, WCLK, WCLKE, WE, WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2
, WADDR_1, WADDR_0, MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0, WDATA_15, WDATA_14, WDATA_13
, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0);
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.135-3173.141" *)
input MASK_0;
wire MASK_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.127-3173.133" *)
input MASK_1;
wire MASK_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.54-3173.61" *)
input MASK_10;
wire MASK_10;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.45-3173.52" *)
input MASK_11;
wire MASK_11;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.36-3173.43" *)
input MASK_12;
wire MASK_12;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.27-3173.34" *)
input MASK_13;
wire MASK_13;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.18-3173.25" *)
input MASK_14;
wire MASK_14;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.9-3173.16" *)
input MASK_15;
wire MASK_15;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.119-3173.125" *)
input MASK_2;
wire MASK_2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.111-3173.117" *)
input MASK_3;
wire MASK_3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.103-3173.109" *)
input MASK_4;
wire MASK_4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.95-3173.101" *)
input MASK_5;
wire MASK_5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.87-3173.93" *)
input MASK_6;
wire MASK_6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.79-3173.85" *)
input MASK_7;
wire MASK_7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.71-3173.77" *)
input MASK_8;
wire MASK_8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3173.63-3173.69" *)
input MASK_9;
wire MASK_9;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.100-3170.107" *)
input RADDR_0;
wire RADDR_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.91-3170.98" *)
input RADDR_1;
wire RADDR_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.9-3170.17" *)
input RADDR_10;
wire RADDR_10;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.82-3170.89" *)
input RADDR_2;
wire RADDR_2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.73-3170.80" *)
input RADDR_3;
wire RADDR_3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.64-3170.71" *)
input RADDR_4;
wire RADDR_4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.55-3170.62" *)
input RADDR_5;
wire RADDR_5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.46-3170.53" *)
input RADDR_6;
wire RADDR_6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.37-3170.44" *)
input RADDR_7;
wire RADDR_7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.28-3170.35" *)
input RADDR_8;
wire RADDR_8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3170.19-3170.26" *)
input RADDR_9;
wire RADDR_9;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3169.9-3169.13" *)
input RCLK;
wire RCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3169.15-3169.20" *)
input RCLKE;
wire RCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.150-3168.157" *)
output RDATA_0;
wire RDATA_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.141-3168.148" *)
output RDATA_1;
wire RDATA_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.59-3168.67" *)
output RDATA_10;
wire RDATA_10;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.49-3168.57" *)
output RDATA_11;
wire RDATA_11;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.39-3168.47" *)
output RDATA_12;
wire RDATA_12;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.29-3168.37" *)
output RDATA_13;
wire RDATA_13;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.19-3168.27" *)
output RDATA_14;
wire RDATA_14;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.9-3168.17" *)
output RDATA_15;
wire RDATA_15;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.132-3168.139" *)
output RDATA_2;
wire RDATA_2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.123-3168.130" *)
output RDATA_3;
wire RDATA_3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.114-3168.121" *)
output RDATA_4;
wire RDATA_4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.105-3168.112" *)
output RDATA_5;
wire RDATA_5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.96-3168.103" *)
output RDATA_6;
wire RDATA_6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.87-3168.94" *)
output RDATA_7;
wire RDATA_7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.78-3168.85" *)
output RDATA_8;
wire RDATA_8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3168.69-3168.76" *)
output RDATA_9;
wire RDATA_9;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3169.22-3169.24" *)
input RE;
wire RE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.100-3172.107" *)
input WADDR_0;
wire WADDR_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.91-3172.98" *)
input WADDR_1;
wire WADDR_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.9-3172.17" *)
input WADDR_10;
wire WADDR_10;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.82-3172.89" *)
input WADDR_2;
wire WADDR_2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.73-3172.80" *)
input WADDR_3;
wire WADDR_3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.64-3172.71" *)
input WADDR_4;
wire WADDR_4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.55-3172.62" *)
input WADDR_5;
wire WADDR_5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.46-3172.53" *)
input WADDR_6;
wire WADDR_6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.37-3172.44" *)
input WADDR_7;
wire WADDR_7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.28-3172.35" *)
input WADDR_8;
wire WADDR_8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3172.19-3172.26" *)
input WADDR_9;
wire WADDR_9;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3171.9-3171.13" *)
input WCLK;
wire WCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3171.15-3171.20" *)
input WCLKE;
wire WCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.150-3174.157" *)
input WDATA_0;
wire WDATA_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.141-3174.148" *)
input WDATA_1;
wire WDATA_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.59-3174.67" *)
input WDATA_10;
wire WDATA_10;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.49-3174.57" *)
input WDATA_11;
wire WDATA_11;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.39-3174.47" *)
input WDATA_12;
wire WDATA_12;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.29-3174.37" *)
input WDATA_13;
wire WDATA_13;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.19-3174.27" *)
input WDATA_14;
wire WDATA_14;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.9-3174.17" *)
input WDATA_15;
wire WDATA_15;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.132-3174.139" *)
input WDATA_2;
wire WDATA_2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.123-3174.130" *)
input WDATA_3;
wire WDATA_3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.114-3174.121" *)
input WDATA_4;
wire WDATA_4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.105-3174.112" *)
input WDATA_5;
wire WDATA_5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.96-3174.103" *)
input WDATA_6;
wire WDATA_6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.87-3174.94" *)
input WDATA_7;
wire WDATA_7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.78-3174.85" *)
input WDATA_8;
wire WDATA_8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3174.69-3174.76" *)
input WDATA_9;
wire WDATA_9;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3171.22-3171.24" *)
input WE;
wire WE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:228.1-260.10" *)
module SB_CARRY(CO, I0, I1, CI);
(* src = "/usr/share/yosys/ice40/cells_sim.v:228.43-228.45" *)
input CI;
wire CI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:228.25-228.27" *)
output CO;
wire CO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:228.35-228.37" *)
input I0;
wire I0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:228.39-228.41" *)
input I1;
wire I1;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:265.1-300.10" *)
module SB_DFF(Q, C, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:267.8-267.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:267.11-267.12" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:266.13-266.14" *)
output Q;
wire Q;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:303.1-347.10" *)
module SB_DFFE(Q, C, E, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:305.8-305.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:307.8-307.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:306.8-306.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:304.13-304.14" *)
output Q;
wire Q;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:653.1-730.10" *)
module SB_DFFER(Q, C, E, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:655.8-655.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:658.8-658.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:656.8-656.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:654.13-654.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:657.8-657.9" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:794.1-871.10" *)
module SB_DFFES(Q, C, E, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:796.8-796.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:799.8-799.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:797.8-797.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:795.13-795.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:798.8-798.9" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:592.1-650.10" *)
module SB_DFFESR(Q, C, E, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:594.8-594.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:597.8-597.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:595.8-595.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:593.13-593.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:596.8-596.9" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:733.1-791.10" *)
module SB_DFFESS(Q, C, E, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:735.8-735.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:738.8-738.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:736.8-736.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:734.13-734.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:737.8-737.9" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:876.1-911.10" *)
module SB_DFFN(Q, C, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:878.8-878.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:878.11-878.12" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:877.13-877.14" *)
output Q;
wire Q;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:914.1-958.10" *)
module SB_DFFNE(Q, C, E, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:916.8-916.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:918.8-918.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:917.8-917.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:915.13-915.14" *)
output Q;
wire Q;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1264.1-1341.10" *)
module SB_DFFNER(Q, C, E, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1266.8-1266.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1269.8-1269.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1267.8-1267.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1265.13-1265.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1268.8-1268.9" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1405.1-1483.10" *)
module SB_DFFNES(Q, C, E, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1407.8-1407.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1410.8-1410.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1408.8-1408.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1406.13-1406.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1409.8-1409.9" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1203.1-1261.10" *)
module SB_DFFNESR(Q, C, E, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1205.8-1205.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1208.8-1208.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1206.8-1206.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1204.13-1204.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1207.8-1207.9" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1344.1-1402.10" *)
module SB_DFFNESS(Q, C, E, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1346.8-1346.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1349.8-1349.9" *)
input D;
wire D;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1347.8-1347.9" *)
input E;
wire E;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1345.13-1345.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1348.8-1348.9" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1011.1-1079.10" *)
module SB_DFFNR(Q, C, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1013.8-1013.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1013.14-1013.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1012.13-1012.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1013.11-1013.12" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1132.1-1200.10" *)
module SB_DFFNS(Q, C, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1134.8-1134.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1134.14-1134.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1133.13-1133.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1134.11-1134.12" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:961.1-1008.10" *)
module SB_DFFNSR(Q, C, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:963.8-963.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:963.14-963.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:962.13-962.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:963.11-963.12" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1082.1-1129.10" *)
module SB_DFFNSS(Q, C, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:1084.8-1084.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1084.14-1084.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1083.13-1083.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1084.11-1084.12" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:400.1-468.10" *)
module SB_DFFR(Q, C, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:402.8-402.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:402.14-402.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:401.13-401.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:402.11-402.12" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_box = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:521.1-589.10" *)
module SB_DFFS(Q, C, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:523.8-523.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:523.14-523.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:522.13-522.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:523.11-523.12" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:350.1-397.10" *)
module SB_DFFSR(Q, C, R, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:352.8-352.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:352.14-352.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:351.13-351.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:352.11-352.12" *)
input R;
wire R;
endmodule
(* blackbox = 1 *)
(* abc9_flop = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:471.1-518.10" *)
module SB_DFFSS(Q, C, S, D);
(* src = "/usr/share/yosys/ice40/cells_sim.v:473.8-473.9" *)
input C;
wire C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:473.14-473.15" *)
input D;
wire D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:472.13-472.14" *)
output Q;
wire Q;
(* src = "/usr/share/yosys/ice40/cells_sim.v:473.11-473.12" *)
input S;
wire S;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2856.1-2860.10" *)
module SB_FILTER_50NS(FILTERIN, FILTEROUT);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2857.8-2857.16" *)
input FILTERIN;
wire FILTERIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2858.9-2858.18" *)
output FILTEROUT;
wire FILTEROUT;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:162.1-172.10" *)
module SB_GB(USER_SIGNAL_TO_GLOBAL_BUFFER, GLOBAL_BUFFER_OUTPUT);
(* src = "/usr/share/yosys/ice40/cells_sim.v:164.9-164.29" *)
output GLOBAL_BUFFER_OUTPUT;
wire GLOBAL_BUFFER_OUTPUT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:163.9-163.37" *)
input USER_SIGNAL_TO_GLOBAL_BUFFER;
wire USER_SIGNAL_TO_GLOBAL_BUFFER;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:123.1-160.10" *)
module SB_GB_IO(PACKAGE_PIN, GLOBAL_BUFFER_OUTPUT, LATCH_INPUT_VALUE, CLOCK_ENABLE, INPUT_CLK, OUTPUT_CLK, OUTPUT_ENABLE, D_OUT_0, D_OUT_1, D_IN_0, D_IN_1);
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:127.9-127.21" *)
input CLOCK_ENABLE;
wire CLOCK_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:133.9-133.15" *)
output D_IN_0;
wire D_IN_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:134.9-134.15" *)
output D_IN_1;
wire D_IN_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:131.9-131.16" *)
input D_OUT_0;
wire D_OUT_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:132.9-132.16" *)
input D_OUT_1;
wire D_OUT_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:125.9-125.29" *)
output GLOBAL_BUFFER_OUTPUT;
wire GLOBAL_BUFFER_OUTPUT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:128.9-128.18" *)
input INPUT_CLK;
wire INPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:126.9-126.26" *)
input LATCH_INPUT_VALUE;
wire LATCH_INPUT_VALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:129.9-129.19" *)
input OUTPUT_CLK;
wire OUTPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:130.9-130.22" *)
input OUTPUT_ENABLE;
wire OUTPUT_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:124.9-124.20" *)
inout PACKAGE_PIN;
wire PACKAGE_PIN;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2664.1-2681.10" *)
module SB_HFOSC(TRIM0, TRIM1, TRIM2, TRIM3, TRIM4, TRIM5, TRIM6, TRIM7, TRIM8, TRIM9, CLKHFPU, CLKHFEN, CLKHF);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2677.9-2677.14" *)
output CLKHF;
wire CLKHF;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2676.8-2676.15" *)
input CLKHFEN;
wire CLKHFEN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2675.8-2675.15" *)
input CLKHFPU;
wire CLKHFPU;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2665.8-2665.13" *)
input TRIM0;
wire TRIM0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2666.8-2666.13" *)
input TRIM1;
wire TRIM1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2667.8-2667.13" *)
input TRIM2;
wire TRIM2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2668.8-2668.13" *)
input TRIM3;
wire TRIM3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2669.8-2669.13" *)
input TRIM4;
wire TRIM4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2670.8-2670.13" *)
input TRIM5;
wire TRIM5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2671.8-2671.13" *)
input TRIM6;
wire TRIM6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2672.8-2672.13" *)
input TRIM7;
wire TRIM7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2673.8-2673.13" *)
input TRIM8;
wire TRIM8;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2674.8-2674.13" *)
input TRIM9;
wire TRIM9;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2733.1-2773.10" *)
module SB_I2C(SBCLKI, SBRWI, SBSTBI, SBADRI7, SBADRI6, SBADRI5, SBADRI4, SBADRI3, SBADRI2, SBADRI1, SBADRI0, SBDATI7, SBDATI6, SBDATI5, SBDATI4, SBDATI3, SBDATI2, SBDATI1, SBDATI0, SCLI, SDAI
, SBDATO7, SBDATO6, SBDATO5, SBDATO4, SBDATO3, SBDATO2, SBDATO1, SBDATO0, SBACKO, I2CIRQ, I2CWKUP, SCLO, SCLOE, SDAO, SDAOE);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2764.9-2764.15" *)
output I2CIRQ;
wire I2CIRQ;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2765.9-2765.16" *)
output I2CWKUP;
wire I2CWKUP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2763.9-2763.15" *)
output SBACKO;
wire SBACKO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2744.9-2744.16" *)
input SBADRI0;
wire SBADRI0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2743.9-2743.16" *)
input SBADRI1;
wire SBADRI1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2742.9-2742.16" *)
input SBADRI2;
wire SBADRI2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2741.9-2741.16" *)
input SBADRI3;
wire SBADRI3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2740.9-2740.16" *)
input SBADRI4;
wire SBADRI4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2739.9-2739.16" *)
input SBADRI5;
wire SBADRI5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2738.9-2738.16" *)
input SBADRI6;
wire SBADRI6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2737.9-2737.16" *)
input SBADRI7;
wire SBADRI7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2734.9-2734.15" *)
input SBCLKI;
wire SBCLKI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2752.9-2752.16" *)
input SBDATI0;
wire SBDATI0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2751.9-2751.16" *)
input SBDATI1;
wire SBDATI1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2750.9-2750.16" *)
input SBDATI2;
wire SBDATI2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2749.9-2749.16" *)
input SBDATI3;
wire SBDATI3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2748.9-2748.16" *)
input SBDATI4;
wire SBDATI4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2747.9-2747.16" *)
input SBDATI5;
wire SBDATI5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2746.9-2746.16" *)
input SBDATI6;
wire SBDATI6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2745.9-2745.16" *)
input SBDATI7;
wire SBDATI7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2762.9-2762.16" *)
output SBDATO0;
wire SBDATO0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2761.9-2761.16" *)
output SBDATO1;
wire SBDATO1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2760.9-2760.16" *)
output SBDATO2;
wire SBDATO2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2759.9-2759.16" *)
output SBDATO3;
wire SBDATO3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2758.9-2758.16" *)
output SBDATO4;
wire SBDATO4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2757.9-2757.16" *)
output SBDATO5;
wire SBDATO5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2756.9-2756.16" *)
output SBDATO6;
wire SBDATO6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2755.9-2755.16" *)
output SBDATO7;
wire SBDATO7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2735.9-2735.14" *)
input SBRWI;
wire SBRWI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2736.9-2736.15" *)
input SBSTBI;
wire SBSTBI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2753.9-2753.13" *)
input SCLI;
wire SCLI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2766.9-2766.13" *)
output SCLO;
wire SCLO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2767.9-2767.14" *)
output SCLOE;
wire SCLOE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2754.9-2754.13" *)
input SDAI;
wire SDAI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2768.9-2768.13" *)
output SDAO;
wire SDAO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2769.9-2769.14" *)
output SDAOE;
wire SDAOE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:17.1-121.10" *)
module SB_IO(PACKAGE_PIN, LATCH_INPUT_VALUE, CLOCK_ENABLE, INPUT_CLK, OUTPUT_CLK, OUTPUT_ENABLE, D_OUT_0, D_OUT_1, D_IN_0, D_IN_1);
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:20.9-20.21" *)
input CLOCK_ENABLE;
wire CLOCK_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:26.9-26.15" *)
output D_IN_0;
wire D_IN_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:27.9-27.15" *)
output D_IN_1;
wire D_IN_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:24.9-24.16" *)
input D_OUT_0;
wire D_OUT_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:25.9-25.16" *)
input D_OUT_1;
wire D_OUT_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:21.9-21.18" *)
input INPUT_CLK;
wire INPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:19.9-19.26" *)
input LATCH_INPUT_VALUE;
wire LATCH_INPUT_VALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:22.9-22.19" *)
input OUTPUT_CLK;
wire OUTPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:23.9-23.22" *)
input OUTPUT_ENABLE;
wire OUTPUT_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:18.9-18.20" *)
inout PACKAGE_PIN;
wire PACKAGE_PIN;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2862.1-2929.10" *)
module SB_IO_I3C(PACKAGE_PIN, LATCH_INPUT_VALUE, CLOCK_ENABLE, INPUT_CLK, OUTPUT_CLK, OUTPUT_ENABLE, D_OUT_0, D_OUT_1, D_IN_0, D_IN_1, PU_ENB, WEAK_PU_ENB);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2865.9-2865.21" *)
input CLOCK_ENABLE;
wire CLOCK_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2871.9-2871.15" *)
output D_IN_0;
wire D_IN_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2872.9-2872.15" *)
output D_IN_1;
wire D_IN_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2869.9-2869.16" *)
input D_OUT_0;
wire D_OUT_0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2870.9-2870.16" *)
input D_OUT_1;
wire D_OUT_1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2866.9-2866.18" *)
input INPUT_CLK;
wire INPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2864.9-2864.26" *)
input LATCH_INPUT_VALUE;
wire LATCH_INPUT_VALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2867.9-2867.19" *)
input OUTPUT_CLK;
wire OUTPUT_CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2868.9-2868.22" *)
input OUTPUT_ENABLE;
wire OUTPUT_ENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2863.9-2863.20" *)
inout PACKAGE_PIN;
wire PACKAGE_PIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2873.9-2873.15" *)
input PU_ENB;
wire PU_ENB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2874.9-2874.20" *)
input WEAK_PU_ENB;
wire WEAK_PU_ENB;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2931.1-2993.10" *)
module SB_IO_OD(PACKAGEPIN, LATCHINPUTVALUE, CLOCKENABLE, INPUTCLK, OUTPUTCLK, OUTPUTENABLE, DOUT1, DOUT0, DIN1, DIN0);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2934.9-2934.20" *)
input CLOCKENABLE;
wire CLOCKENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2941.9-2941.13" *)
output DIN0;
wire DIN0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2940.9-2940.13" *)
output DIN1;
wire DIN1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2939.9-2939.14" *)
input DOUT0;
wire DOUT0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2938.9-2938.14" *)
input DOUT1;
wire DOUT1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2935.9-2935.17" *)
input INPUTCLK;
wire INPUTCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2933.9-2933.24" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2936.9-2936.18" *)
input OUTPUTCLK;
wire OUTPUTCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2937.9-2937.21" *)
input OUTPUTENABLE;
wire OUTPUTENABLE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2932.9-2932.19" *)
inout PACKAGEPIN;
wire PACKAGEPIN;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2830.1-2853.10" *)
module SB_LEDDA_IP(LEDDCS, LEDDCLK, LEDDDAT7, LEDDDAT6, LEDDDAT5, LEDDDAT4, LEDDDAT3, LEDDDAT2, LEDDDAT1, LEDDDAT0, LEDDADDR3, LEDDADDR2, LEDDADDR1, LEDDADDR0, LEDDDEN, LEDDEXE, LEDDRST, PWMOUT0, PWMOUT1, PWMOUT2, LEDDON
);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2844.8-2844.17" *)
input LEDDADDR0;
wire LEDDADDR0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2843.8-2843.17" *)
input LEDDADDR1;
wire LEDDADDR1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2842.8-2842.17" *)
input LEDDADDR2;
wire LEDDADDR2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2841.8-2841.17" *)
input LEDDADDR3;
wire LEDDADDR3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2832.8-2832.15" *)
input LEDDCLK;
wire LEDDCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2831.8-2831.14" *)
input LEDDCS;
wire LEDDCS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2840.8-2840.16" *)
input LEDDDAT0;
wire LEDDDAT0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2839.8-2839.16" *)
input LEDDDAT1;
wire LEDDDAT1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2838.8-2838.16" *)
input LEDDDAT2;
wire LEDDDAT2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2837.8-2837.16" *)
input LEDDDAT3;
wire LEDDDAT3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2836.8-2836.16" *)
input LEDDDAT4;
wire LEDDDAT4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2835.8-2835.16" *)
input LEDDDAT5;
wire LEDDDAT5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2834.8-2834.16" *)
input LEDDDAT6;
wire LEDDDAT6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2833.8-2833.16" *)
input LEDDDAT7;
wire LEDDDAT7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2845.8-2845.15" *)
input LEDDDEN;
wire LEDDDEN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2846.8-2846.15" *)
input LEDDEXE;
wire LEDDEXE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2851.9-2851.15" *)
output LEDDON;
wire LEDDON;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2847.8-2847.15" *)
input LEDDRST;
wire LEDDRST;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2848.9-2848.16" *)
output PWMOUT0;
wire PWMOUT0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2849.9-2849.16" *)
output PWMOUT1;
wire PWMOUT1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2850.9-2850.16" *)
output PWMOUT2;
wire PWMOUT2;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2709.1-2713.10" *)
module SB_LED_DRV_CUR(EN, LEDPU);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2710.8-2710.10" *)
input EN;
wire EN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2711.9-2711.14" *)
output LEDPU;
wire LEDPU;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2684.1-2689.10" *)
module SB_LFOSC(CLKLFPU, CLKLFEN, CLKLF);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2687.9-2687.14" *)
output CLKLF;
wire CLKLF;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2686.8-2686.15" *)
input CLKLFEN;
wire CLKLFEN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2685.8-2685.15" *)
input CLKLFPU;
wire CLKLFPU;
endmodule
(* blackbox = 1 *)
(* abc9_lut = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:177.1-225.10" *)
module SB_LUT4(O, I0, I1, I2, I3);
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:179.8-179.10" *)
input I0;
wire I0;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:180.8-180.10" *)
input I1;
wire I1;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:181.8-181.10" *)
input I2;
wire I2;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:182.8-182.10" *)
input I3;
wire I3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:178.9-178.10" *)
output O;
wire O;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2996.1-3164.10" *)
module SB_MAC16(CLK, CE, C, A, B, D, AHOLD, BHOLD, CHOLD, DHOLD, IRSTTOP, IRSTBOT, ORSTTOP, ORSTBOT, OLOADTOP, OLOADBOT, ADDSUBTOP, ADDSUBBOT, OHOLDTOP, OHOLDBOT, CI
, ACCUMCI, SIGNEXTIN, O, CO, ACCUMCO, SIGNEXTOUT);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2998.18-2998.19" *)
input [15:0] A;
wire [15:0] A;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3005.12-3005.19" *)
input ACCUMCI;
wire ACCUMCI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3007.13-3007.20" *)
output ACCUMCO;
wire ACCUMCO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3003.19-3003.28" *)
input ADDSUBBOT;
wire ADDSUBBOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3003.8-3003.17" *)
input ADDSUBTOP;
wire ADDSUBTOP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2999.8-2999.13" *)
input AHOLD;
wire AHOLD;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2998.21-2998.22" *)
input [15:0] B;
wire [15:0] B;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2999.15-2999.20" *)
input BHOLD;
wire BHOLD;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2998.15-2998.16" *)
input [15:0] C;
wire [15:0] C;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2997.13-2997.15" *)
input CE;
wire CE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2999.22-2999.27" *)
input CHOLD;
wire CHOLD;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3005.8-3005.10" *)
input CI;
wire CI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2997.8-2997.11" *)
input CLK;
wire CLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3007.9-3007.11" *)
output CO;
wire CO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2998.24-2998.25" *)
input [15:0] D;
wire [15:0] D;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2999.29-2999.34" *)
input DHOLD;
wire DHOLD;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3000.17-3000.24" *)
input IRSTBOT;
wire IRSTBOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3000.8-3000.15" *)
input IRSTTOP;
wire IRSTTOP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3006.16-3006.17" *)
output [31:0] O;
wire [31:0] O;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3004.18-3004.26" *)
input OHOLDBOT;
wire OHOLDBOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3004.8-3004.16" *)
input OHOLDTOP;
wire OHOLDTOP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3002.18-3002.26" *)
input OLOADBOT;
wire OLOADBOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3002.8-3002.16" *)
input OLOADTOP;
wire OLOADTOP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3001.17-3001.24" *)
input ORSTBOT;
wire ORSTBOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3001.8-3001.15" *)
input ORSTTOP;
wire ORSTTOP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3005.21-3005.30" *)
input SIGNEXTIN;
wire SIGNEXTIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:3007.22-3007.32" *)
output SIGNEXTOUT;
wire SIGNEXTOUT;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2521.1-2553.10" *)
module SB_PLL40_2F_CORE(REFERENCECLK, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, LATCHINPUTVALUE, SDO, SDI, SCLK);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2530.10-2530.16" *)
input BYPASS;
wire BYPASS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2528.16-2528.28" *)
input [7:0] DYNAMICDELAY;
wire [7:0] DYNAMICDELAY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2527.10-2527.21" *)
input EXTFEEDBACK;
wire EXTFEEDBACK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2532.10-2532.25" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2529.10-2529.14" *)
output LOCK;
wire LOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2523.10-2523.21" *)
output PLLOUTCOREA;
wire PLLOUTCOREA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2525.10-2525.21" *)
output PLLOUTCOREB;
wire PLLOUTCOREB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2524.10-2524.23" *)
output PLLOUTGLOBALA;
wire PLLOUTGLOBALA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2526.10-2526.23" *)
output PLLOUTGLOBALB;
wire PLLOUTGLOBALB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2522.10-2522.22" *)
input REFERENCECLK;
wire REFERENCECLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2531.10-2531.16" *)
input RESETB;
wire RESETB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2535.10-2535.14" *)
input SCLK;
wire SCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2534.10-2534.13" *)
input SDI;
wire SDI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2533.10-2533.13" *)
output SDO;
wire SDO;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2556.1-2588.10" *)
module SB_PLL40_2F_PAD(PACKAGEPIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, LATCHINPUTVALUE, SDO, SDI, SCLK);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2565.10-2565.16" *)
input BYPASS;
wire BYPASS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2563.16-2563.28" *)
input [7:0] DYNAMICDELAY;
wire [7:0] DYNAMICDELAY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2562.10-2562.21" *)
input EXTFEEDBACK;
wire EXTFEEDBACK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2567.10-2567.25" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2564.10-2564.14" *)
output LOCK;
wire LOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2557.10-2557.20" *)
input PACKAGEPIN;
wire PACKAGEPIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2558.10-2558.21" *)
output PLLOUTCOREA;
wire PLLOUTCOREA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2560.10-2560.21" *)
output PLLOUTCOREB;
wire PLLOUTCOREB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2559.10-2559.23" *)
output PLLOUTGLOBALA;
wire PLLOUTGLOBALA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2561.10-2561.23" *)
output PLLOUTGLOBALB;
wire PLLOUTGLOBALB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2566.10-2566.16" *)
input RESETB;
wire RESETB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2570.10-2570.14" *)
input SCLK;
wire SCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2569.10-2569.13" *)
input SDI;
wire SDI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2568.10-2568.13" *)
output SDO;
wire SDO;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2487.1-2518.10" *)
module SB_PLL40_2_PAD(PACKAGEPIN, PLLOUTCOREA, PLLOUTGLOBALA, PLLOUTCOREB, PLLOUTGLOBALB, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, LATCHINPUTVALUE, SDO, SDI, SCLK);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2496.10-2496.16" *)
input BYPASS;
wire BYPASS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2494.16-2494.28" *)
input [7:0] DYNAMICDELAY;
wire [7:0] DYNAMICDELAY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2493.10-2493.21" *)
input EXTFEEDBACK;
wire EXTFEEDBACK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2498.10-2498.25" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2495.10-2495.14" *)
output LOCK;
wire LOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2488.10-2488.20" *)
input PACKAGEPIN;
wire PACKAGEPIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2489.10-2489.21" *)
output PLLOUTCOREA;
wire PLLOUTCOREA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2491.10-2491.21" *)
output PLLOUTCOREB;
wire PLLOUTCOREB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2490.10-2490.23" *)
output PLLOUTGLOBALA;
wire PLLOUTGLOBALA;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2492.10-2492.23" *)
output PLLOUTGLOBALB;
wire PLLOUTGLOBALB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2497.10-2497.16" *)
input RESETB;
wire RESETB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2501.10-2501.14" *)
input SCLK;
wire SCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2500.10-2500.13" *)
input SDI;
wire SDI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2499.10-2499.13" *)
output SDO;
wire SDO;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2425.1-2453.10" *)
module SB_PLL40_CORE(REFERENCECLK, PLLOUTCORE, PLLOUTGLOBAL, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, LATCHINPUTVALUE, SDO, SDI, SCLK);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2432.10-2432.16" *)
input BYPASS;
wire BYPASS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2430.16-2430.28" *)
input [7:0] DYNAMICDELAY;
wire [7:0] DYNAMICDELAY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2429.10-2429.21" *)
input EXTFEEDBACK;
wire EXTFEEDBACK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2434.10-2434.25" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2431.10-2431.14" *)
output LOCK;
wire LOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2427.10-2427.20" *)
output PLLOUTCORE;
wire PLLOUTCORE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2428.10-2428.22" *)
output PLLOUTGLOBAL;
wire PLLOUTGLOBAL;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2426.10-2426.22" *)
input REFERENCECLK;
wire REFERENCECLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2433.10-2433.16" *)
input RESETB;
wire RESETB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2437.10-2437.14" *)
input SCLK;
wire SCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2436.10-2436.13" *)
input SDI;
wire SDI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2435.10-2435.13" *)
output SDO;
wire SDO;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2456.1-2484.10" *)
module SB_PLL40_PAD(PACKAGEPIN, PLLOUTCORE, PLLOUTGLOBAL, EXTFEEDBACK, DYNAMICDELAY, LOCK, BYPASS, RESETB, LATCHINPUTVALUE, SDO, SDI, SCLK);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2463.10-2463.16" *)
input BYPASS;
wire BYPASS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2461.16-2461.28" *)
input [7:0] DYNAMICDELAY;
wire [7:0] DYNAMICDELAY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2460.10-2460.21" *)
input EXTFEEDBACK;
wire EXTFEEDBACK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2465.10-2465.25" *)
input LATCHINPUTVALUE;
wire LATCHINPUTVALUE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2462.10-2462.14" *)
output LOCK;
wire LOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2457.10-2457.20" *)
input PACKAGEPIN;
wire PACKAGEPIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2458.10-2458.20" *)
output PLLOUTCORE;
wire PLLOUTCORE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2459.10-2459.22" *)
output PLLOUTGLOBAL;
wire PLLOUTGLOBAL;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2464.10-2464.16" *)
input RESETB;
wire RESETB;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2468.10-2468.14" *)
input SCLK;
wire SCLK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2467.10-2467.13" *)
input SDI;
wire SDI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2466.10-2466.13" *)
output SDO;
wire SDO;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1487.1-1724.10" *)
module SB_RAM40_4K(RDATA, RCLK, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA);
(* defaultvalue = 16'h0000 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1497.16-1497.20" *)
input [15:0] MASK;
wire [15:0] MASK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1492.16-1492.21" *)
input [10:0] RADDR;
wire [10:0] RADDR;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1489.16-1489.20" *)
input RCLK;
wire RCLK;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1490.16-1490.21" *)
input RCLKE;
wire RCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1488.16-1488.21" *)
output [15:0] RDATA;
wire [15:0] RDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1491.16-1491.18" *)
input RE;
wire RE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1496.16-1496.21" *)
input [10:0] WADDR;
wire [10:0] WADDR;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1493.16-1493.20" *)
input WCLK;
wire WCLK;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1494.16-1494.21" *)
input WCLKE;
wire WCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1498.16-1498.21" *)
input [15:0] WDATA;
wire [15:0] WDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1495.16-1495.18" *)
input WE;
wire WE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1726.1-1860.10" *)
module SB_RAM40_4KNR(RDATA, RCLKN, RCLKE, RE, RADDR, WCLK, WCLKE, WE, WADDR, MASK, WDATA);
(* defaultvalue = 16'h0000 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1736.16-1736.20" *)
input [15:0] MASK;
wire [15:0] MASK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1731.16-1731.21" *)
input [10:0] RADDR;
wire [10:0] RADDR;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1729.16-1729.21" *)
input RCLKE;
wire RCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1728.16-1728.21" *)
input RCLKN;
wire RCLKN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1727.16-1727.21" *)
output [15:0] RDATA;
wire [15:0] RDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1730.16-1730.18" *)
input RE;
wire RE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1735.16-1735.21" *)
input [10:0] WADDR;
wire [10:0] WADDR;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1732.16-1732.20" *)
input WCLK;
wire WCLK;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1733.16-1733.21" *)
input WCLKE;
wire WCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1737.16-1737.21" *)
input [15:0] WDATA;
wire [15:0] WDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1734.16-1734.18" *)
input WE;
wire WE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1998.1-2132.10" *)
module SB_RAM40_4KNRNW(RDATA, RCLKN, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA);
(* defaultvalue = 16'h0000 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2008.16-2008.20" *)
input [15:0] MASK;
wire [15:0] MASK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2003.16-2003.21" *)
input [10:0] RADDR;
wire [10:0] RADDR;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2001.16-2001.21" *)
input RCLKE;
wire RCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2000.16-2000.21" *)
input RCLKN;
wire RCLKN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1999.16-1999.21" *)
output [15:0] RDATA;
wire [15:0] RDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2002.16-2002.18" *)
input RE;
wire RE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2007.16-2007.21" *)
input [10:0] WADDR;
wire [10:0] WADDR;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2005.16-2005.21" *)
input WCLKE;
wire WCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2004.16-2004.21" *)
input WCLKN;
wire WCLKN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2009.16-2009.21" *)
input [15:0] WDATA;
wire [15:0] WDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2006.16-2006.18" *)
input WE;
wire WE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1862.1-1996.10" *)
module SB_RAM40_4KNW(RDATA, RCLK, RCLKE, RE, RADDR, WCLKN, WCLKE, WE, WADDR, MASK, WDATA);
(* defaultvalue = 16'h0000 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1872.16-1872.20" *)
input [15:0] MASK;
wire [15:0] MASK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1867.16-1867.21" *)
input [10:0] RADDR;
wire [10:0] RADDR;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1864.16-1864.20" *)
input RCLK;
wire RCLK;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1865.16-1865.21" *)
input RCLKE;
wire RCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1863.16-1863.21" *)
output [15:0] RDATA;
wire [15:0] RDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1866.16-1866.18" *)
input RE;
wire RE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1871.16-1871.21" *)
input [10:0] WADDR;
wire [10:0] WADDR;
(* defaultvalue = 1'h1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1869.16-1869.21" *)
input WCLKE;
wire WCLKE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1868.16-1868.21" *)
input WCLKN;
wire WCLKN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:1873.16-1873.21" *)
input [15:0] WDATA;
wire [15:0] WDATA;
(* defaultvalue = 1'h0 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:1870.16-1870.18" *)
input WE;
wire WE;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2692.1-2706.10" *)
module SB_RGBA_DRV(CURREN, RGBLEDEN, RGB0PWM, RGB1PWM, RGB2PWM, RGB0, RGB1, RGB2);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2693.8-2693.14" *)
input CURREN;
wire CURREN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2698.9-2698.13" *)
output RGB0;
wire RGB0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2695.8-2695.15" *)
input RGB0PWM;
wire RGB0PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2699.9-2699.13" *)
output RGB1;
wire RGB1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2696.8-2696.15" *)
input RGB1PWM;
wire RGB1PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2700.9-2700.13" *)
output RGB2;
wire RGB2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2697.8-2697.15" *)
input RGB2PWM;
wire RGB2PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2694.8-2694.16" *)
input RGBLEDEN;
wire RGBLEDEN;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2716.1-2730.10" *)
module SB_RGB_DRV(RGBLEDEN, RGB0PWM, RGB1PWM, RGB2PWM, RGBPU, RGB0, RGB1, RGB2);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2722.9-2722.13" *)
output RGB0;
wire RGB0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2718.8-2718.15" *)
input RGB0PWM;
wire RGB0PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2723.9-2723.13" *)
output RGB1;
wire RGB1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2719.8-2719.15" *)
input RGB1PWM;
wire RGB1PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2724.9-2724.13" *)
output RGB2;
wire RGB2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2720.8-2720.15" *)
input RGB2PWM;
wire RGB2PWM;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2717.8-2717.16" *)
input RGBLEDEN;
wire RGBLEDEN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2721.8-2721.13" *)
input RGBPU;
wire RGBPU;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2776.1-2827.10" *)
module SB_SPI(SBCLKI, SBRWI, SBSTBI, SBADRI7, SBADRI6, SBADRI5, SBADRI4, SBADRI3, SBADRI2, SBADRI1, SBADRI0, SBDATI7, SBDATI6, SBDATI5, SBDATI4, SBDATI3, SBDATI2, SBDATI1, SBDATI0, MI, SI
, SCKI, SCSNI, SBDATO7, SBDATO6, SBDATO5, SBDATO4, SBDATO3, SBDATO2, SBDATO1, SBDATO0, SBACKO, SPIIRQ, SPIWKUP, SO, SOE, MO, MOE, SCKO, SCKOE, MCSNO3, MCSNO2
, MCSNO1, MCSNO0, MCSNOE3, MCSNOE2, MCSNOE1, MCSNOE0);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2820.9-2820.15" *)
output MCSNO0;
wire MCSNO0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2819.9-2819.15" *)
output MCSNO1;
wire MCSNO1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2818.9-2818.15" *)
output MCSNO2;
wire MCSNO2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2817.9-2817.15" *)
output MCSNO3;
wire MCSNO3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2824.9-2824.16" *)
output MCSNOE0;
wire MCSNOE0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2823.9-2823.16" *)
output MCSNOE1;
wire MCSNOE1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2822.9-2822.16" *)
output MCSNOE2;
wire MCSNOE2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2821.9-2821.16" *)
output MCSNOE3;
wire MCSNOE3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2796.9-2796.11" *)
input MI;
wire MI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2813.9-2813.11" *)
output MO;
wire MO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2814.9-2814.12" *)
output MOE;
wire MOE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2808.9-2808.15" *)
output SBACKO;
wire SBACKO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2787.9-2787.16" *)
input SBADRI0;
wire SBADRI0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2786.9-2786.16" *)
input SBADRI1;
wire SBADRI1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2785.9-2785.16" *)
input SBADRI2;
wire SBADRI2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2784.9-2784.16" *)
input SBADRI3;
wire SBADRI3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2783.9-2783.16" *)
input SBADRI4;
wire SBADRI4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2782.9-2782.16" *)
input SBADRI5;
wire SBADRI5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2781.9-2781.16" *)
input SBADRI6;
wire SBADRI6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2780.9-2780.16" *)
input SBADRI7;
wire SBADRI7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2777.9-2777.15" *)
input SBCLKI;
wire SBCLKI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2795.9-2795.16" *)
input SBDATI0;
wire SBDATI0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2794.9-2794.16" *)
input SBDATI1;
wire SBDATI1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2793.9-2793.16" *)
input SBDATI2;
wire SBDATI2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2792.9-2792.16" *)
input SBDATI3;
wire SBDATI3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2791.9-2791.16" *)
input SBDATI4;
wire SBDATI4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2790.9-2790.16" *)
input SBDATI5;
wire SBDATI5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2789.9-2789.16" *)
input SBDATI6;
wire SBDATI6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2788.9-2788.16" *)
input SBDATI7;
wire SBDATI7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2807.9-2807.16" *)
output SBDATO0;
wire SBDATO0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2806.9-2806.16" *)
output SBDATO1;
wire SBDATO1;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2805.9-2805.16" *)
output SBDATO2;
wire SBDATO2;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2804.9-2804.16" *)
output SBDATO3;
wire SBDATO3;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2803.9-2803.16" *)
output SBDATO4;
wire SBDATO4;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2802.9-2802.16" *)
output SBDATO5;
wire SBDATO5;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2801.9-2801.16" *)
output SBDATO6;
wire SBDATO6;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2800.9-2800.16" *)
output SBDATO7;
wire SBDATO7;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2778.9-2778.14" *)
input SBRWI;
wire SBRWI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2779.9-2779.15" *)
input SBSTBI;
wire SBSTBI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2798.9-2798.13" *)
input SCKI;
wire SCKI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2815.9-2815.13" *)
output SCKO;
wire SCKO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2816.9-2816.14" *)
output SCKOE;
wire SCKOE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2799.9-2799.14" *)
input SCSNI;
wire SCSNI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2797.9-2797.11" *)
input SI;
wire SI;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2811.9-2811.11" *)
output SO;
wire SO;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2812.9-2812.12" *)
output SOE;
wire SOE;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2809.9-2809.15" *)
output SPIIRQ;
wire SPIIRQ;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2810.9-2810.16" *)
output SPIWKUP;
wire SPIWKUP;
endmodule
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2600.1-2661.10" *)
module SB_SPRAM256KA(ADDRESS, DATAIN, MASKWREN, WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF, DATAOUT);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2601.15-2601.22" *)
input [13:0] ADDRESS;
wire [13:0] ADDRESS;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.14-2604.24" *)
input CHIPSELECT;
wire CHIPSELECT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.26-2604.31" *)
input CLOCK;
wire CLOCK;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2602.15-2602.21" *)
input [15:0] DATAIN;
wire [15:0] DATAIN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2605.20-2605.27" *)
output [15:0] DATAOUT;
wire [15:0] DATAOUT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2603.14-2603.22" *)
input [3:0] MASKWREN;
wire [3:0] MASKWREN;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.49-2604.57" *)
input POWEROFF;
wire POWEROFF;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.42-2604.47" *)
input SLEEP;
wire SLEEP;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.33-2604.40" *)
input STANDBY;
wire STANDBY;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2604.8-2604.12" *)
input WREN;
wire WREN;
endmodule
(* keep = 1 *)
(* blackbox = 1 *)
(* cells_not_processed = 1 *)
(* src = "/usr/share/yosys/ice40/cells_sim.v:2593.1-2598.10" *)
module SB_WARMBOOT(BOOT, S1, S0);
(* src = "/usr/share/yosys/ice40/cells_sim.v:2594.8-2594.12" *)
input BOOT;
wire BOOT;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2596.8-2596.10" *)
input S0;
wire S0;
(* src = "/usr/share/yosys/ice40/cells_sim.v:2595.8-2595.10" *)
input S1;
wire S1;
endmodule
Raw
test.post.v
/* Generated by Yosys 0.19 (git sha1 a45c131b3, gcc 12.1.0 -march=x86-64 -mtune=generic -O2 -fstack-protector-strong -fno-plt -fPIC -Os) */
(* top = 1 *)
(* src = "test.v:1.1-10.10" *)
module top(q, d, clk);
(* ROUTING = {0{1'b0}} *)
wire _0_;
(* ROUTING = {0{1'b0}} *)
wire _1_;
(* ROUTING = {0{1'b0}} *)
input clk;
wire clk;
(* ROUTING = "X13/Y9/io_0:D_IN_0;;1;X12/Y9/sp4_h_r_0;X13/Y9/13.9.io_0:D_IN_0.->.12.9.sp4_h_r_0;1;X13/Y9/local_g1_0;X13/Y9/12.9.sp4_h_r_0.->.13.9.local_g1_0;1;X13/Y9/fabout;X13/Y9/13.9.local_g1_0.->.13.9.fabout;1" *)
(* src = "test.v:2.8-2.11" *)
wire \clk$SB_IO_IN ;
(* ROUTING = "X0/Y1/glb_netwk_2;;1;X2/Y16/lutff_global:clk;X2/Y16/0.1.glb_netwk_2.->.2.16.lutff_global:clk;1" *)
wire \clk$SB_IO_IN_$glb_clk ;
(* ROUTING = {0{1'b0}} *)
input d;
wire d;
(* ROUTING = "X2/Y17/io_1:D_IN_0;;1;X2/Y16/local_g0_2;X2/Y16/2.17.io_1:D_IN_0.->.2.16.local_g0_2;1;X2/Y16/lutff_1:in_3;X2/Y16/2.16.local_g0_2.->.2.16.lutff_1:in_3;1;X2/Y16/lutff_1:in_3_lut;X2/Y16/2.16.lutff_1:in_3.->.2.16.lutff_1:in_3_lut;1" *)
(* src = "test.v:2.13-2.14" *)
wire \d$SB_IO_IN ;
(* ROUTING = {0{1'b0}} *)
output q;
wire q;
(* ROUTING = "X2/Y17/local_g1_1;X2/Y17/2.16.lutff_1:out.->.2.17.local_g1_1;1;X2/Y17/io_0:D_OUT_0;X2/Y17/2.17.local_g1_1.->.2.17.io_0:D_OUT_0;1;X2/Y16/lutff_1:out;;1;X2/Y16/local_g3_1;X2/Y16/2.16.lutff_1:out.->.2.16.local_g3_1;1;X2/Y16/lutff_1:in_1;X2/Y16/2.16.local_g3_1.->.2.16.lutff_1:in_1;1;X2/Y16/lutff_1:in_2_lut;X2/Y16/2.16.lutff_1:in_1.->.2.16.lutff_1:in_2_lut;1" *)
(* src = "test.v:3.13-3.14" *)
wire \q$SB_IO_OUT ;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X4/Y12/lc4" *)
ICESTORM_LC _2_ (
.O(_0_)
);
defparam _2_.ASYNC_SR = 1'h0;
defparam _2_.CARRY_ENABLE = 1'h0;
defparam _2_.CIN_CONST = 1'h0;
defparam _2_.CIN_SET = 1'h0;
defparam _2_.DFF_ENABLE = 1'h0;
defparam _2_.LUT_INIT = 16'h0000;
defparam _2_.NEG_CLK = 1'h0;
defparam _2_.SET_NORESET = 1'h0;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X12/Y9/lc7" *)
ICESTORM_LC _3_ (
.O(_1_)
);
defparam _3_.ASYNC_SR = 1'h0;
defparam _3_.CARRY_ENABLE = 1'h0;
defparam _3_.CIN_CONST = 1'h0;
defparam _3_.CIN_SET = 1'h0;
defparam _3_.DFF_ENABLE = 1'h0;
defparam _3_.LUT_INIT = 16'h0001;
defparam _3_.NEG_CLK = 1'h0;
defparam _3_.SET_NORESET = 1'h0;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X13/Y9/gb" *)
SB_GB _4_ (
.GLOBAL_BUFFER_OUTPUT(\clk$SB_IO_IN_$glb_clk ),
.USER_SIGNAL_TO_GLOBAL_BUFFER(\clk$SB_IO_IN )
);
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X13/Y9/io0" *)
(* src = "test.v:2.8-2.11" *)
SB_IO \clk$sb_io (
.D_IN_0(\clk$SB_IO_IN ),
.PACKAGE_PIN(clk)
);
defparam \clk$sb_io .IO_STANDARD = "SB_LVCMOS";
defparam \clk$sb_io .NEG_TRIGGER = 1'h0;
defparam \clk$sb_io .PIN_TYPE = 32'd1;
defparam \clk$sb_io .PULLUP = 1'h0;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X2/Y17/io1" *)
(* src = "test.v:2.13-2.14" *)
SB_IO \d$sb_io (
.D_IN_0(\d$SB_IO_IN ),
.PACKAGE_PIN(d)
);
defparam \d$sb_io .IO_STANDARD = "SB_LVCMOS";
defparam \d$sb_io .NEG_TRIGGER = 1'h0;
defparam \d$sb_io .PIN_TYPE = 32'd1;
defparam \d$sb_io .PULLUP = 1'h0;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X2/Y16/lc1" *)
(* module_not_derived = 32'd1 *)
(* src = "test.v:7.2-8.14|/usr/bin/../share/yosys/ice40/ff_map.v:2.51-2.90" *)
ICESTORM_LC d_SB_LUT4_I3_LC (
.CLK(\clk$SB_IO_IN_$glb_clk ),
.I2(\q$SB_IO_OUT ),
.I3(\d$SB_IO_IN ),
.O(\q$SB_IO_OUT )
);
defparam d_SB_LUT4_I3_LC.ASYNC_SR = 1'h0;
defparam d_SB_LUT4_I3_LC.CARRY_ENABLE = 1'h0;
defparam d_SB_LUT4_I3_LC.CIN_CONST = 1'h0;
defparam d_SB_LUT4_I3_LC.CIN_SET = 1'h0;
defparam d_SB_LUT4_I3_LC.DFF_ENABLE = 1'h1;
defparam d_SB_LUT4_I3_LC.LUT_INIT = 16'h0ff0;
defparam d_SB_LUT4_I3_LC.NEG_CLK = 1'h0;
defparam d_SB_LUT4_I3_LC.SET_NORESET = 1'h0;
(* BEL_STRENGTH = 32'd1 *)
(* NEXTPNR_BEL = "X2/Y17/io0" *)
(* src = "test.v:3.13-3.14" *)
SB_IO \q$sb_io (
.D_OUT_0(\q$SB_IO_OUT ),
.PACKAGE_PIN(q)
);
defparam \q$sb_io .IO_STANDARD = "SB_LVCMOS";
defparam \q$sb_io .NEG_TRIGGER = 1'h0;
defparam \q$sb_io .PIN_TYPE = 32'd25;
defparam \q$sb_io .PULLUP = 1'h0;
endmodule
Raw
test.sdf
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "top")
(VENDOR "nextpnr")
(PROGRAM "nextpnr")
(DIVIDER /)
(TIMESCALE 1ps)
(CELL
(CELLTYPE "top")
(INSTANCE )
(DELAY
(ABSOLUTE
(INTERCONNECT \$gbuf_clk\$SB_IO_IN_\$glb_clk/GLOBAL_BUFFER_OUTPUT d_SB_LUT4_I3_LC/CLK (308:308:308) (308:308:308))
(INTERCONNECT clk\$sb_io/D_IN_0 \$gbuf_clk\$SB_IO_IN_\$glb_clk/USER_SIGNAL_TO_GLOBAL_BUFFER (644:644:644) (644:644:644))
(INTERCONNECT d\$sb_io/D_IN_0 d_SB_LUT4_I3_LC/I3 (588:588:588) (588:588:588))
(INTERCONNECT d_SB_LUT4_I3_LC/O d_SB_LUT4_I3_LC/I2 (588:588:588) (588:588:588))
(INTERCONNECT d_SB_LUT4_I3_LC/O q\$sb_io/D_OUT_0 (588:588:588) (588:588:588))
)
)
)
(CELL
(CELLTYPE "SB_GB")
(INSTANCE \$gbuf_clk\$SB_IO_IN_\$glb_clk)
(DELAY
(ABSOLUTE
(IOPATH USER_SIGNAL_TO_GLOBAL_BUFFER GLOBAL_BUFFER_OUTPUT (617:617:617) (617:617:617))
)
)
)
(CELL
(CELLTYPE "ICESTORM_LC")
(INSTANCE d_SB_LUT4_I3_LC)
(DELAY
(ABSOLUTE
(IOPATH CLK O (540:540:540) (540:540:540))
)
)
(TIMINGCHECK
(SETUPHOLD (posedge I3) (posedge CLK) (335:335:335) (0:0:0))
(SETUPHOLD (negedge I3) (posedge CLK) (335:335:335) (0:0:0))
(SETUPHOLD (posedge I2) (posedge CLK) (398:398:398) (0:0:0))
(SETUPHOLD (negedge I2) (posedge CLK) (398:398:398) (0:0:0))
)
)
(CELL
(CELLTYPE "SB_IO")
(INSTANCE clk\$sb_io)
)
(CELL
(CELLTYPE "SB_IO")
(INSTANCE d\$sb_io)
)
(CELL
(CELLTYPE "ICESTORM_LC")
(INSTANCE \$PACKER_GND)
)
(CELL
(CELLTYPE "ICESTORM_LC")
(INSTANCE \$PACKER_VCC)
)
(CELL
(CELLTYPE "SB_IO")
(INSTANCE q\$sb_io)
)
)
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