Logsys XILINX Kintex-7 FPGA PCIe development Board

Logsys_XILINX_Kintex-7_FPGA_PCIe_development_Board.md

0. Introduction

Contains notes about a Logsys XILINX Kintex-7 FPGA PCIe development Board

Logsys XILINX Kintex7 Kintex-7 FPGA PCIe development Board FOR PARTS OR REPAIR is the ebay listing which contained:

Doesn't show up the interface in the PCI device list ( should shoup as 0x10EE 0x7011 ) . Leds show activity .

Looking at the pictures in the listing was powered up in a PCI with JP1 set to JTAG for the configuration mode, so that might explain the lack of enumerating as a PCIe endpoint.

LOGSYS_Kintex7_FPGA_Board.pdf is a manual found, in Hungarian. Has schematics so should allow constraints to be determined.

1. As delivered state

Moved the JP1 jumper from JTAG to SPI. Fitted the card to a Dell Optiplex XE4. The device hasn't enumerated as a PCI endpoint.

Connect a USB cable from the PC to the USB B mini port on the card. The manual indicates the USB B mini port can attempt to power the card, so haven't yet attempted to connect the USB port on the card to a different PC.

The Vivado Lab Edition 2026.1 detected a XCK70T device, which wasn't reported as programmed. The Boot mode pins M[2:0] are 001 which is Master Serial configuration mode, so the device should have attempted to boot from the SPI flash.

In Vivado Lab Edition added a mt25ql512-spi-x1_x2_x4 configuration device. Read back the configuration device, and parse_bitstream_file parses what appears to be valid bitstream for a 7K70T:

$ ~/fpga_sio/software_tests/eclipse_project/bin/release/xilinx_quad_spi/parse_bitstream_file ~/Downloads/Logsys_original.mcs 
Successfully parsed bitstream of length 3011324 bytes with 546 configuration packets
Read bitsteam from file /home/mr_halfword/Downloads/Logsys_original.mcs
Sync word at byte index 0x30
  Type 1 packet opcode NOP
  Type 1 packet opcode write register TIMER words 00000000
  Type 1 packet opcode write register WBSTAR words 00000000
  Type 1 packet opcode write register CMD command NULL
  Type 1 packet opcode NOP
  Type 1 packet opcode write register CMD command RCRC
  Type 1 packet opcode NOP (2 consecutive)
  Type 1 packet opcode write register RBCRC_SW words 00000000
  Type 1 packet opcode write register COR0 words 02003FE5
  Type 1 packet opcode write register COR1 words 00000000
  Type 1 packet opcode write register IDCODE 7K70T
  Type 1 packet opcode write register CMD command SWITCH
  Type 1 packet opcode NOP
  Type 1 packet opcode write register MASK words 00000401
  Type 1 packet opcode write register CTL0 words 00000501
  Type 1 packet opcode write register MASK words 00000000
  Type 1 packet opcode write register CTL1 words 00000000
  Type 1 packet opcode NOP (8 consecutive)
  Configuration data writes consisting of:
    1 NOPs
    1 FAR writes
    1 WCFG commands
    1 FDRI writes with a total of 0 words
    1 Type 2 packets with a total of 752248 words
  Type 1 packet opcode write register CRC words 6302D493
  Type 1 packet opcode NOP (2 consecutive)
  Type 1 packet opcode write register CMD command GRESTORE
  Type 1 packet opcode NOP
  Type 1 packet opcode write register CMD command DGHIGH_LFRM
  Type 1 packet opcode NOP (100 consecutive)
  Type 1 packet opcode write register CMD command START
  Type 1 packet opcode NOP
  Type 1 packet opcode write register FAR words 03BE0000
  Type 1 packet opcode write register MASK words 00000501
  Type 1 packet opcode write register CTL0 words 00000501
  Type 1 packet opcode write register CRC words E3AD7EA5
  Type 1 packet opcode NOP (2 consecutive)
  Type 1 packet opcode write register CMD command DESYNC
  Type 1 packet opcode NOP (400 consecutive)

There is no heatsink on the FPGA and after the PC has been on for 38 minutes the XADC is reporting a maximum temperature of 86.1C.

In Vivado Lab Edition attempted to boot from the configuration device, but failed to boot.

2. Board appears broken

Created a LOGSYS_70T_enum project, with a PCIe endpoint. Fails to enumerate in the Dell Optiplex XE4.

Used the Vivado Lab Edition 2026.1 to program the SPI configuration flash. The flash contents verifies OK, but the FPGA still fails to boot from the configuration flash.

On powering up the PC with the cover removed, the PWROK LED is off. The PWROK signal is connected to the FPGA_INITn signal via an invertor.

Therefore, the board appears to have a failure on one or more supply rails.