Contains notes about XCKU5P Board FPGA Core Board Onboard 128Mbit FLASH FMC QSFP28 100G Port PCIE3.0
The board picture above show the Micron DDR4 devices have a FBGA Code of D9WFM which is MT40A512M16LY-062E-IT-E which is a 8Gb component. The XCKU5P-FFVB676.pdf schematic gives the part number of U1 and U11 as MT40A512M16LY-062E-IT-E, which matches. The XCKU5P-FFVB676.rar contained a datasheet named MT40A512M16LY-062E ITE.pdf, but was actually for 4Gb components. For now, assume MT40A512M16LY-062E-IT-E is the correct DDR4 part
Read the Device DNA over JTAG and using AMD Device Lookup reports:
| Device | XCKU5P |
| Package-Pin | FFVB676 |
| Revision Code | AAZ |
| SpeedGrade | 2I |
The linked ebay page contains:
- Two 5070 packaged 100MHz active differential crystal oscillators, one-channel for GT transceiver and one-channel for system logic.
The picture of the back of the PCB shows two 6-pin oscillators marked E100.000.
After obtained a download link to XCKU5P-FFVB676.rar from the seller, the schematic shows:
- The QSFP socket is connected to MGT227
- A SG7050VAN-100.000000M-KEGA3 connected to MGT227_CLK0_N and MGT227_CLK0_P. This is LVDS output.
PG203 for the UltraScale+ Devices Integrated 100G Ethernet Subsystem v3.1 lists the valid reference clocks as:
- 103.12 MHz
- 128.90 MHz
- 156.25 MHz
- 161.13 MHz
- 195.31 MHz
- 201.41 MHz
- 206.25 MHz
- 257.81 MHz
- 309.37 MHz
- 312.50 MHz
- 322.266 MHz
On trying to set a 100 MHz reference clock using a TCL command for a CMAC in Vivado 2025.2 got the following error. I.e. a reduced set of valid frequencies compared to what PG203 specified:
Valid values are - 156.25, 161.1328125, 195.3125, 201.4160156, 257.8125, 312.5, 322.265625
While it is for something else, How to run 10G Ethernet with 125MHz transceiver reference clock? might provide a clue about how to use a non-standard reference clock frequency.
Fitted in a Dell Optiplex XE4 and connected JTAG.
The Vivado Hardware Manager showed a design loaded with two ILAs and a MIG:
XCKU5P-FFVB676/Demo/XCKU5P_PCIe_DDR4_ETH/vivado/XCKU5P_PCIe_DDR4_ETH.runs/impl_1/DDR_PCIE_ETH_TOP.ltx in the download for the board has the UUIDs which match the the ILAs and MIG in the loaded design.
The loaded design has enumerated as a gen3x8 PCIe endpoint:
$ dump_info/dump_pci_info_pciutils
domain=0000 bus=01 dev=00 func=00 rev=00
vendor_id=10ee (Xilinx Corporation) device_id=9038 (Device 9038) subvendor_id=10ee subdevice_id=0007
iommu_group=12
control: I/O- Mem+ BusMaster- ParErr- SERR- DisINTx-
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
bar[0] base_addr=70700000 size=10000 is_IO=0 is_prefetchable=0 is_64=0
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] Message Signaled Interrupts
Capabilities: [70] PCI Express v2 Express Endpoint, MSI 0
Link capabilities: Max speed 8 GT/s Max width x8
Negotiated link status: Current speed 8 GT/s Width x8
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s
DevCap: MaxPayload 1024 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 75.000W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
LnkCap: Port # 0 ASPM not supported
L0s Exit Latency More than 4 μs
L1 Exit Latency More than 64 μs
ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- ABWMgmt-
LnkSta: TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [100 v1] Advanced Error Reporting
Capabilities: [1c0 v1] Secondary PCIe Capability
domain=0000 bus=00 dev=01 func=00 rev=05
vendor_id=8086 (Intel Corporation) device_id=460d (12th Gen Core Processor PCI Express x16 Controller #1)
iommu_group=2
driver=pcieport
control: I/O+ Mem+ BusMaster+ ParErr- SERR+ DisINTx+
status: INTx- <ParErr- >TAbort- <TAbort- <MAbort- >SERR- DetParErr-
Capabilities: [40] PCI Express v2 Root Port, MSI 0
Link capabilities: Max speed 16 GT/s Max width x16
Negotiated link status: Current speed 8 GT/s Width x8
Link capabilities2: Supported link speeds 2.5 GT/s 5.0 GT/s 8.0 GT/s 16.0 GT/s
DevCap: MaxPayload 256 bytes PhantFunc 0 Latency L0s Maximum of 64 ns L1 Maximum of 1 μs
ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend-
LnkCap: Port # 2 ASPM L1
L0s Exit Latency 2 μs to 4 μs
L1 Exit Latency 8 μs to less than 16 μs
ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
LnkCtl: ASPM Disabled RCB 64 bytes Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt+ ABWMgmt+
LnkSta: TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
Slot #2 PowerLimit 75.000W Interlock- NoCompl+
Capabilities: [80] Message Signaled Interrupts
Capabilities: [98] Bridge subsystem vendor/device ID
Capabilities: [a0] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [100 v1] Advanced Error Reporting
Capabilities: [220 v1] Access Control Services
Capabilities: [200 v1] L1 PM Substates
Capabilities: [150 v1] Precision Time Measurement
Capabilities: [a30 v1] Secondary PCIe Capability
Capabilities: [a90 v1] Data Link Feature
Capabilities: [a9c v1] Physical Layer 16.0 GT/s
Capabilities: [edc v1] Lane Margining at Receiver
Capabilities: [adc v1] Physical Layer 32.0 GT/s
Capabilities: [b0c v1] Alternate Protocol
The XCKU5P_PCIe_DDR4_ETH example project was created in Vivado 2019.2. Opening in Vivado 2025.2 and selecting to upgrade can see:
- XMDA PCIe endpoint.
- XDMA configured as AXI Memory Mapped with a single DMA channel.
- M_AXI of XMDA connected to MIG which has 2 GB of DDR4 memory. Where 2 GB is based upon the configured memory devices.
- XDMA PCIe to AXI Lite Master Interface is disabled.
- As a result, only XMDA registers are memory mapped, into BAR 0.
Made a temporary modification to add this design to the software, as a XMDA device with attached memory.
Detects the XDMA OK, with the expected single channel:
$ identify_pcie_fpga_design/display_identified_pcie_fpga_designs
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Design XCKU5P_PCIe_DDR4_ETH:
PCI device 0000:01:00.0 rev 00 IOMMU group 12
DMA bridge bar 0 memory base offset 0x0 size 0x20000000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
However, attempts to access the memory fail with incorrect contents. I.e. the DMA transfers appear to complete but the first word in memory checked has the incorrect contents:
esting using 4 buffers of size 0x8000000 bytes, H2C channel 0 C2H channel 0
TEST FAIL:
C2H failure : DDR word[0] actual=0xffffffff expected=0x0
Testing XCKU5P_PCIe_DDR4_ETH design with memory base address 0x0 size 0x20000000
PCI device 0000:01:00.0 IOMMU group 12
Testing using:
H2C channel 0 transfer length 0x10000000 bytes with 4 descriptors
C2H channel 0 transfer length 0x10000000 bytes with 4 descriptors
TEST FAIL:
C2H failure : DDR word[0] actual=0xfdfdffff expected=0x0
Overall FAIL
$ xilinx_dma_bridge_for_pcie/test_dma_descriptor_credits
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Testing DMA bridge bar 0 memory base offset 0x0 size 0x20000000
Testing 12570624 bytes of card memory, using rings with 1023 descriptors, and a total of 3069 descriptors
card_words[0] actual=0xcec6e793 expected=0x00000000
Test: FAIL
On looking at the XCKU5P_PCIe_DDR4_ETH example project which was converted to Vivado 2025.2 the address map shows only 512M of memory. Initially set the software to expect 2G of memory, and after finding address map changed the software to only expect 512M. That didn't change the failures.
If commented out the check on the data values in test_dma_descriptor_credits then passed, so all the DMA transfers completed.
The Vivado Hardware Manager verified the mt25qu128-spi-x1_x2_x4 configuration device contents matched XCKU5P_PCIe_DDR4_ETH/vivado/XCKU5P_PCIe_DDR4_ETH.runs/impl_1/DDR_PCIE_ETH_TOP.mcs in the example project.
Not sure what causes the incorrect data. Suggest created a design for the board from scratch to see if can re-create the problem. As a result of the failures, didn't commit the software changes.
When first looked at the Vivado 2025.2 Hardware Manager view of the MIG only saw a status of CAL PASS which assumed was error free.
The full MIG Core Properties are the following:
2D_EYE_SCAN_END 000
2D_EYE_SCAN_START 000
BISC_ALIGN_NQTR_NIBBLE0 000
BISC_ALIGN_NQTR_NIBBLE1 000
BISC_ALIGN_NQTR_NIBBLE2 000
BISC_ALIGN_NQTR_NIBBLE3 000
BISC_ALIGN_NQTR_NIBBLE4 000
BISC_ALIGN_NQTR_NIBBLE5 000
BISC_ALIGN_NQTR_NIBBLE6 000
BISC_ALIGN_NQTR_NIBBLE7 000
BISC_ALIGN_PQTR_NIBBLE0 00c
BISC_ALIGN_PQTR_NIBBLE1 002
BISC_ALIGN_PQTR_NIBBLE2 00b
BISC_ALIGN_PQTR_NIBBLE3 001
BISC_ALIGN_PQTR_NIBBLE4 00c
BISC_ALIGN_PQTR_NIBBLE5 000
BISC_ALIGN_PQTR_NIBBLE6 00b
BISC_ALIGN_PQTR_NIBBLE7 003
BISC_NQTR_NIBBLE0 03c
BISC_NQTR_NIBBLE1 03f
BISC_NQTR_NIBBLE2 03f
BISC_NQTR_NIBBLE3 03f
BISC_NQTR_NIBBLE4 03d
BISC_NQTR_NIBBLE5 03d
BISC_NQTR_NIBBLE6 03d
BISC_NQTR_NIBBLE7 03f
BISC_PQTR_NIBBLE0 048
BISC_PQTR_NIBBLE1 03e
BISC_PQTR_NIBBLE2 046
BISC_PQTR_NIBBLE3 03f
BISC_PQTR_NIBBLE4 049
BISC_PQTR_NIBBLE5 03f
BISC_PQTR_NIBBLE6 046
BISC_PQTR_NIBBLE7 040
BITS_PER_BYTES 008
BIT_TIME 417
BUS_DATA_BURST_0_BIT_0 000
BUS_DATA_BURST_0_BIT_1 000
BUS_DATA_BURST_0_BIT_2 000
BUS_DATA_BURST_0_BIT_3 000
BUS_DATA_BURST_0_BIT_4 000
BUS_DATA_BURST_0_BIT_5 000
BUS_DATA_BURST_0_BIT_6 000
BUS_DATA_BURST_0_BIT_7 000
BUS_DATA_BURST_1_BIT_0 000
BUS_DATA_BURST_1_BIT_1 000
BUS_DATA_BURST_1_BIT_2 000
BUS_DATA_BURST_1_BIT_3 000
BUS_DATA_BURST_1_BIT_4 000
BUS_DATA_BURST_1_BIT_5 000
BUS_DATA_BURST_1_BIT_6 000
BUS_DATA_BURST_1_BIT_7 000
BUS_DATA_BURST_2_BIT_0 000
BUS_DATA_BURST_2_BIT_1 000
BUS_DATA_BURST_2_BIT_2 000
BUS_DATA_BURST_2_BIT_3 000
BUS_DATA_BURST_2_BIT_4 000
BUS_DATA_BURST_2_BIT_5 000
BUS_DATA_BURST_2_BIT_6 000
BUS_DATA_BURST_2_BIT_7 000
BUS_DATA_BURST_3_BIT_0 000
BUS_DATA_BURST_3_BIT_1 000
BUS_DATA_BURST_3_BIT_2 000
BUS_DATA_BURST_3_BIT_3 000
BUS_DATA_BURST_3_BIT_4 000
BUS_DATA_BURST_3_BIT_5 000
BUS_DATA_BURST_3_BIT_6 000
BUS_DATA_BURST_3_BIT_7 000
BYTES 004
CAL_ERROR_MSG No errors detected during calibration.
CAL_MAP_VERSION 001
CAL_STATUS_SIZE 007
CAL_STOP_MARGIN FALSE
CAL_VERSION_C_MB 00b
CAL_VERSION_RTL 007
CELL_NAME N/A
CLASS hw_mig
CONFIG_INFORMATION_0 0d1
CONFIG_INFORMATION_1 049
CONFIG_INFORMATION_2 004
CONFIG_INFORMATION_3 010
CONFIG_INFORMATION_4 032
CONFIG_INFORMATION_5 049
CONFIG_INFORMATION_6 048
CONFIG_INFORMATION_7 049
CONFIG_INFORMATION_8 0a0
CONFIG_INFORMATION_9 001
CONFIG_INFORMATION_10 014
CONFIG_INFORMATION_11 004
CONFIG_INFORMATION_12 004
CONFIG_INFORMATION_13 004
CONFIG_INFORMATION_14 029
CONFIG_INFORMATION_15 001
CONFIG_INFORMATION_16 000
CONFIG_INFORMATION_17 000
CONFIG_INFORMATION_18 000
CONFIG_INFORMATION_19 021
CONFIG_INFORMATION_20 000
CONFIG_INFORMATION_21 000
CONFIG_INFORMATION_22 000
CONFIG_INFORMATION_23 001
CONFIG_INFORMATION_24 000
CONFIG_INFORMATION_25 001
CONFIG_INFORMATION_26 000
CONFIG_INFORMATION_27 000
CONFIG_INFORMATION_28 000
CONFIG_INFORMATION_29 030
CONFIG_INFORMATION_30 040
CONFIG_INFORMATION_31 050
CONFIG_INFORMATION_32 139
CONTROLLER_INFO 000
CORE_UUID 3AFCAFB7E94F59F8BC65E9AE44BCBA9A
DBG_END 001
DDR_CAL_ERROR_0 000
DDR_CAL_ERROR_1 001
DDR_CAL_ERROR_CODE 001
DDR_CAL_STATUS_RANK0_0 0ff
DDR_CAL_STATUS_RANK0_1 1fe
DDR_CAL_STATUS_RANK0_2 1cf
DDR_CAL_STATUS_RANK0_3 01f
DDR_CAL_STATUS_RANK0_4 03f
DDR_CAL_STATUS_RANK0_5 000
DDR_CAL_STATUS_RANK0_6 000
DDR_CAL_STATUS_RANK1_0 000
DDR_CAL_STATUS_RANK1_1 000
DDR_CAL_STATUS_RANK1_2 000
DDR_CAL_STATUS_RANK1_3 000
DDR_CAL_STATUS_RANK1_4 000
DDR_CAL_STATUS_RANK1_5 000
DDR_CAL_STATUS_RANK1_6 000
DDR_CAL_STATUS_RANK2_0 000
DDR_CAL_STATUS_RANK2_1 000
DDR_CAL_STATUS_RANK2_2 000
DDR_CAL_STATUS_RANK2_3 000
DDR_CAL_STATUS_RANK2_4 000
DDR_CAL_STATUS_RANK2_5 000
DDR_CAL_STATUS_RANK2_6 000
DDR_CAL_STATUS_RANK3_0 000
DDR_CAL_STATUS_RANK3_1 000
DDR_CAL_STATUS_RANK3_2 000
DDR_CAL_STATUS_RANK3_3 000
DDR_CAL_STATUS_RANK3_4 000
DDR_CAL_STATUS_RANK3_5 000
DDR_CAL_STATUS_RANK3_6 000
DDR_POST_CAL_STATUS_0 004
DDR_POST_CAL_STATUS_1 000
DDR_POST_CAL_STATUS_2 000
DDR_PRE_CAL_STATUS 01f
DISPLAY_NAME MIG_1
DQS_GATE_COARSE_RANK0_BYTE0 005
DQS_GATE_COARSE_RANK0_BYTE1 005
DQS_GATE_COARSE_RANK0_BYTE2 004
DQS_GATE_COARSE_RANK0_BYTE3 004
DQS_GATE_FINE_CENTER_RANK0_BYTE0 018
DQS_GATE_FINE_CENTER_RANK0_BYTE1 018
DQS_GATE_FINE_CENTER_RANK0_BYTE2 018
DQS_GATE_FINE_CENTER_RANK0_BYTE3 01b
DQS_GATE_FINE_LEFT_RANK0_BYTE0 016
DQS_GATE_FINE_LEFT_RANK0_BYTE1 015
DQS_GATE_FINE_LEFT_RANK0_BYTE2 015
DQS_GATE_FINE_LEFT_RANK0_BYTE3 019
DQS_GATE_FINE_RIGHT_RANK0_BYTE0 01a
DQS_GATE_FINE_RIGHT_RANK0_BYTE1 01b
DQS_GATE_FINE_RIGHT_RANK0_BYTE2 01b
DQS_GATE_FINE_RIGHT_RANK0_BYTE3 01e
DQS_GATE_PATTERN_0_RANK0_BYTE0 0c0
DQS_GATE_PATTERN_0_RANK0_BYTE1 0c0
DQS_GATE_PATTERN_0_RANK0_BYTE2 060
DQS_GATE_PATTERN_0_RANK0_BYTE3 060
DQS_GATE_PATTERN_1_RANK0_BYTE0 006
DQS_GATE_PATTERN_1_RANK0_BYTE1 006
DQS_GATE_PATTERN_1_RANK0_BYTE2 003
DQS_GATE_PATTERN_1_RANK0_BYTE3 003
DQS_GATE_PATTERN_2_RANK0_BYTE0 000
DQS_GATE_PATTERN_2_RANK0_BYTE1 000
DQS_GATE_PATTERN_2_RANK0_BYTE2 000
DQS_GATE_PATTERN_2_RANK0_BYTE3 000
DQS_GATE_READ_LATENCY_RANK0_BYTE0 011
DQS_GATE_READ_LATENCY_RANK0_BYTE1 011
DQS_GATE_READ_LATENCY_RANK0_BYTE2 011
DQS_GATE_READ_LATENCY_RANK0_BYTE3 011
DQS_GATE_TRACKING FAIL : Underflow of the coarse taps used for tracking. Error found on Rank 0, Byte 1.
DQS_TRACK_COARSE_MAX_RANK0_BYTE0 005
DQS_TRACK_COARSE_MAX_RANK0_BYTE1 005
DQS_TRACK_COARSE_MAX_RANK0_BYTE2 004
DQS_TRACK_COARSE_MAX_RANK0_BYTE3 004
DQS_TRACK_COARSE_MIN_RANK0_BYTE0 001
DQS_TRACK_COARSE_MIN_RANK0_BYTE1 000
DQS_TRACK_COARSE_MIN_RANK0_BYTE2 004
DQS_TRACK_COARSE_MIN_RANK0_BYTE3 004
DQS_TRACK_COARSE_RANK0_BYTE0 001
DQS_TRACK_COARSE_RANK0_BYTE1 000
DQS_TRACK_COARSE_RANK0_BYTE2 004
DQS_TRACK_COARSE_RANK0_BYTE3 004
DQS_TRACK_FINE_MAX_RANK0_BYTE0 03c
DQS_TRACK_FINE_MAX_RANK0_BYTE1 03d
DQS_TRACK_FINE_MAX_RANK0_BYTE2 019
DQS_TRACK_FINE_MAX_RANK0_BYTE3 01d
DQS_TRACK_FINE_MIN_RANK0_BYTE0 000
DQS_TRACK_FINE_MIN_RANK0_BYTE1 000
DQS_TRACK_FINE_MIN_RANK0_BYTE2 017
DQS_TRACK_FINE_MIN_RANK0_BYTE3 01a
DQS_TRACK_FINE_RANK0_BYTE0 027
DQS_TRACK_FINE_RANK0_BYTE1 000
DQS_TRACK_FINE_RANK0_BYTE2 018
DQS_TRACK_FINE_RANK0_BYTE3 01b
END_ADDR0 041
END_ADDR1 002
ERROR_MAP_VERSION 001
HWM_TOOL_VER 2025.2
MEMORY_CODE_NAME 000
MEMORY_FREQUENCY_0 141
MEMORY_FREQUENCY_1 001
MEMORY_MODULE_TYPE 001
MEMORY_VOLTAGE 001
MEM_TYPE 002
MICROBLAZE_START_UP PASS
MIG_REFRESH_RATE 3000
MMCM_D 001
MMCM_M 00f
MR0_0 164
MR0_1 005
MR1_0 101
MR1_1 001
MR2_0 018
MR2_1 000
MR3_0 000
MR3_1 001
MR4_0 000
MR4_1 000
MR5_0 000
MR5_1 002
MR6_0 014
MR6_1 004
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE0 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE1 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE2 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE3 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE0 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE1 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE2 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE3 000
NAME localhost:3121/xilinx_tcf/Digilent/210512180081/0_1/MIG_1
NIBBLES 008
NUM_RANK 001
PERIOD 833
PLL_D 001
PLL_M 004
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE0 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE1 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE2 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE3 000
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT0 036
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT1 043
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT2 047
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT3 04c
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT4 03a
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT5 03c
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT6 044
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT7 036
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT0 03e
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT1 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT2 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT3 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT4 042
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT5 03a
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT6 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT7 043
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT0 04a
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT1 04b
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT2 050
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT3 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT4 04c
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT5 044
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT6 047
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT7 043
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT0 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT1 040
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT2 04b
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT3 048
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT4 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT5 03e
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT6 040
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT7 042
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE0 04a
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE1 043
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE2 042
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE3 045
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE4 04b
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE5 04b
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE6 046
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE7 046
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE0 021
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE1 01a
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE2 018
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE3 01b
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE4 020
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE5 022
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE6 01b
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE7 01d
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE0 073
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE1 06d
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE2 06d
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE3 06f
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE4 077
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE5 074
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE6 072
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE7 06f
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE0 05a
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE1 048
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE2 050
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE3 04a
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE4 05a
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE5 050
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE6 053
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE7 04a
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE0 031
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE1 01f
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE2 022
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE3 01e
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE4 032
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE5 027
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE6 028
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE7 020
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE0 084
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE1 071
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE2 07e
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE3 077
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE4 082
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE5 079
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE6 07e
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE7 074
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE0 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE1 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE2 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE3 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE0 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE1 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE2 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE3 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE0 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE1 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE2 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE3 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE0 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE1 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE2 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE3 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE0 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE1 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE2 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE3 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE0 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE1 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE2 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE3 000
RDLVL_DESKEW_DBI_IDELAY_BYTE0 000
RDLVL_DESKEW_DBI_IDELAY_BYTE1 000
RDLVL_DESKEW_DBI_IDELAY_BYTE2 000
RDLVL_DESKEW_DBI_IDELAY_BYTE3 000
RDLVL_DESKEW_DBI_NQTR_BYTE0 000
RDLVL_DESKEW_DBI_NQTR_BYTE1 000
RDLVL_DESKEW_DBI_NQTR_BYTE2 000
RDLVL_DESKEW_DBI_NQTR_BYTE3 000
RDLVL_DESKEW_DBI_PQTR_BYTE0 000
RDLVL_DESKEW_DBI_PQTR_BYTE1 000
RDLVL_DESKEW_DBI_PQTR_BYTE2 000
RDLVL_DESKEW_DBI_PQTR_BYTE3 000
RDLVL_DESKEW_IDELAY_BYTE0_BIT0 021
RDLVL_DESKEW_IDELAY_BYTE0_BIT1 02d
RDLVL_DESKEW_IDELAY_BYTE0_BIT2 02d
RDLVL_DESKEW_IDELAY_BYTE0_BIT3 030
RDLVL_DESKEW_IDELAY_BYTE0_BIT4 026
RDLVL_DESKEW_IDELAY_BYTE0_BIT5 02a
RDLVL_DESKEW_IDELAY_BYTE0_BIT6 02c
RDLVL_DESKEW_IDELAY_BYTE0_BIT7 022
RDLVL_DESKEW_IDELAY_BYTE1_BIT0 02f
RDLVL_DESKEW_IDELAY_BYTE1_BIT1 032
RDLVL_DESKEW_IDELAY_BYTE1_BIT2 035
RDLVL_DESKEW_IDELAY_BYTE1_BIT3 034
RDLVL_DESKEW_IDELAY_BYTE1_BIT4 033
RDLVL_DESKEW_IDELAY_BYTE1_BIT5 026
RDLVL_DESKEW_IDELAY_BYTE1_BIT6 032
RDLVL_DESKEW_IDELAY_BYTE1_BIT7 02f
RDLVL_DESKEW_IDELAY_BYTE2_BIT0 02d
RDLVL_DESKEW_IDELAY_BYTE2_BIT1 030
RDLVL_DESKEW_IDELAY_BYTE2_BIT2 036
RDLVL_DESKEW_IDELAY_BYTE2_BIT3 02b
RDLVL_DESKEW_IDELAY_BYTE2_BIT4 032
RDLVL_DESKEW_IDELAY_BYTE2_BIT5 025
RDLVL_DESKEW_IDELAY_BYTE2_BIT6 02b
RDLVL_DESKEW_IDELAY_BYTE2_BIT7 029
RDLVL_DESKEW_IDELAY_BYTE3_BIT0 02d
RDLVL_DESKEW_IDELAY_BYTE3_BIT1 028
RDLVL_DESKEW_IDELAY_BYTE3_BIT2 034
RDLVL_DESKEW_IDELAY_BYTE3_BIT3 032
RDLVL_DESKEW_IDELAY_BYTE3_BIT4 02e
RDLVL_DESKEW_IDELAY_BYTE3_BIT5 02b
RDLVL_DESKEW_IDELAY_BYTE3_BIT6 02c
RDLVL_DESKEW_IDELAY_BYTE3_BIT7 02c
RDLVL_DESKEW_NQTR_NIBBLE0 000
RDLVL_DESKEW_NQTR_NIBBLE1 001
RDLVL_DESKEW_NQTR_NIBBLE2 000
RDLVL_DESKEW_NQTR_NIBBLE3 000
RDLVL_DESKEW_NQTR_NIBBLE4 000
RDLVL_DESKEW_NQTR_NIBBLE5 000
RDLVL_DESKEW_NQTR_NIBBLE6 000
RDLVL_DESKEW_NQTR_NIBBLE7 000
RDLVL_DESKEW_PQTR_NIBBLE0 00c
RDLVL_DESKEW_PQTR_NIBBLE1 000
RDLVL_DESKEW_PQTR_NIBBLE2 007
RDLVL_DESKEW_PQTR_NIBBLE3 000
RDLVL_DESKEW_PQTR_NIBBLE4 00c
RDLVL_DESKEW_PQTR_NIBBLE5 002
RDLVL_DESKEW_PQTR_NIBBLE6 009
RDLVL_DESKEW_PQTR_NIBBLE7 001
RDLVL_IDELAY_DBI_FINAL_BYTE0 000
RDLVL_IDELAY_DBI_FINAL_BYTE1 000
RDLVL_IDELAY_DBI_FINAL_BYTE2 000
RDLVL_IDELAY_DBI_FINAL_BYTE3 000
RDLVL_IDELAY_DBI_RANK0_BYTE0 000
RDLVL_IDELAY_DBI_RANK0_BYTE1 000
RDLVL_IDELAY_DBI_RANK0_BYTE2 000
RDLVL_IDELAY_DBI_RANK0_BYTE3 000
RDLVL_IDELAY_FINAL_BYTE0_BIT0 036
RDLVL_IDELAY_FINAL_BYTE0_BIT1 043
RDLVL_IDELAY_FINAL_BYTE0_BIT2 047
RDLVL_IDELAY_FINAL_BYTE0_BIT3 04c
RDLVL_IDELAY_FINAL_BYTE0_BIT4 03a
RDLVL_IDELAY_FINAL_BYTE0_BIT5 03c
RDLVL_IDELAY_FINAL_BYTE0_BIT6 044
RDLVL_IDELAY_FINAL_BYTE0_BIT7 036
RDLVL_IDELAY_FINAL_BYTE1_BIT0 03e
RDLVL_IDELAY_FINAL_BYTE1_BIT1 046
RDLVL_IDELAY_FINAL_BYTE1_BIT2 046
RDLVL_IDELAY_FINAL_BYTE1_BIT3 045
RDLVL_IDELAY_FINAL_BYTE1_BIT4 042
RDLVL_IDELAY_FINAL_BYTE1_BIT5 03a
RDLVL_IDELAY_FINAL_BYTE1_BIT6 045
RDLVL_IDELAY_FINAL_BYTE1_BIT7 043
RDLVL_IDELAY_FINAL_BYTE2_BIT0 04a
RDLVL_IDELAY_FINAL_BYTE2_BIT1 04b
RDLVL_IDELAY_FINAL_BYTE2_BIT2 050
RDLVL_IDELAY_FINAL_BYTE2_BIT3 045
RDLVL_IDELAY_FINAL_BYTE2_BIT4 04c
RDLVL_IDELAY_FINAL_BYTE2_BIT5 044
RDLVL_IDELAY_FINAL_BYTE2_BIT6 047
RDLVL_IDELAY_FINAL_BYTE2_BIT7 043
RDLVL_IDELAY_FINAL_BYTE3_BIT0 046
RDLVL_IDELAY_FINAL_BYTE3_BIT1 040
RDLVL_IDELAY_FINAL_BYTE3_BIT2 04b
RDLVL_IDELAY_FINAL_BYTE3_BIT3 048
RDLVL_IDELAY_FINAL_BYTE3_BIT4 046
RDLVL_IDELAY_FINAL_BYTE3_BIT5 03e
RDLVL_IDELAY_FINAL_BYTE3_BIT6 040
RDLVL_IDELAY_FINAL_BYTE3_BIT7 042
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT0 036
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT1 043
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT2 047
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT3 04c
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT4 03a
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT5 03c
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT6 044
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT7 036
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT0 03e
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT1 046
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT2 046
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT3 045
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT4 042
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT5 03a
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT6 045
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT7 043
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT0 049
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT1 04a
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT2 04f
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT3 045
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT4 04b
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT5 044
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT6 047
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT7 043
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT0 046
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT1 040
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT2 04b
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT3 048
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT4 046
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT5 03e
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT6 040
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT7 042
RDLVL_NQTR_CENTER_FINAL_NIBBLE0 04a
RDLVL_NQTR_CENTER_FINAL_NIBBLE1 043
RDLVL_NQTR_CENTER_FINAL_NIBBLE2 042
RDLVL_NQTR_CENTER_FINAL_NIBBLE3 045
RDLVL_NQTR_CENTER_FINAL_NIBBLE4 04b
RDLVL_NQTR_CENTER_FINAL_NIBBLE5 04b
RDLVL_NQTR_CENTER_FINAL_NIBBLE6 046
RDLVL_NQTR_CENTER_FINAL_NIBBLE7 046
RDLVL_NQTR_CENTER_RANK0_NIBBLE0 04f
RDLVL_NQTR_CENTER_RANK0_NIBBLE1 048
RDLVL_NQTR_CENTER_RANK0_NIBBLE2 048
RDLVL_NQTR_CENTER_RANK0_NIBBLE3 04b
RDLVL_NQTR_CENTER_RANK0_NIBBLE4 04f
RDLVL_NQTR_CENTER_RANK0_NIBBLE5 050
RDLVL_NQTR_CENTER_RANK0_NIBBLE6 04a
RDLVL_NQTR_CENTER_RANK0_NIBBLE7 04b
RDLVL_NQTR_LEFT_RANK0_NIBBLE0 01e
RDLVL_NQTR_LEFT_RANK0_NIBBLE1 017
RDLVL_NQTR_LEFT_RANK0_NIBBLE2 016
RDLVL_NQTR_LEFT_RANK0_NIBBLE3 019
RDLVL_NQTR_LEFT_RANK0_NIBBLE4 01f
RDLVL_NQTR_LEFT_RANK0_NIBBLE5 01f
RDLVL_NQTR_LEFT_RANK0_NIBBLE6 018
RDLVL_NQTR_LEFT_RANK0_NIBBLE7 01b
RDLVL_NQTR_RIGHT_RANK0_NIBBLE0 080
RDLVL_NQTR_RIGHT_RANK0_NIBBLE1 07a
RDLVL_NQTR_RIGHT_RANK0_NIBBLE2 07a
RDLVL_NQTR_RIGHT_RANK0_NIBBLE3 07d
RDLVL_NQTR_RIGHT_RANK0_NIBBLE4 07f
RDLVL_NQTR_RIGHT_RANK0_NIBBLE5 081
RDLVL_NQTR_RIGHT_RANK0_NIBBLE6 07c
RDLVL_NQTR_RIGHT_RANK0_NIBBLE7 07b
RDLVL_PQTR_CENTER_FINAL_NIBBLE0 05a
RDLVL_PQTR_CENTER_FINAL_NIBBLE1 048
RDLVL_PQTR_CENTER_FINAL_NIBBLE2 050
RDLVL_PQTR_CENTER_FINAL_NIBBLE3 04a
RDLVL_PQTR_CENTER_FINAL_NIBBLE4 05a
RDLVL_PQTR_CENTER_FINAL_NIBBLE5 050
RDLVL_PQTR_CENTER_FINAL_NIBBLE6 053
RDLVL_PQTR_CENTER_FINAL_NIBBLE7 04a
RDLVL_PQTR_CENTER_RANK0_NIBBLE0 058
RDLVL_PQTR_CENTER_RANK0_NIBBLE1 048
RDLVL_PQTR_CENTER_RANK0_NIBBLE2 04f
RDLVL_PQTR_CENTER_RANK0_NIBBLE3 04a
RDLVL_PQTR_CENTER_RANK0_NIBBLE4 05c
RDLVL_PQTR_CENTER_RANK0_NIBBLE5 053
RDLVL_PQTR_CENTER_RANK0_NIBBLE6 053
RDLVL_PQTR_CENTER_RANK0_NIBBLE7 049
RDLVL_PQTR_LEFT_RANK0_NIBBLE0 016
RDLVL_PQTR_LEFT_RANK0_NIBBLE1 008
RDLVL_PQTR_LEFT_RANK0_NIBBLE2 00e
RDLVL_PQTR_LEFT_RANK0_NIBBLE3 00a
RDLVL_PQTR_LEFT_RANK0_NIBBLE4 01a
RDLVL_PQTR_LEFT_RANK0_NIBBLE5 012
RDLVL_PQTR_LEFT_RANK0_NIBBLE6 010
RDLVL_PQTR_LEFT_RANK0_NIBBLE7 006
RDLVL_PQTR_RIGHT_RANK0_NIBBLE0 09a
RDLVL_PQTR_RIGHT_RANK0_NIBBLE1 089
RDLVL_PQTR_RIGHT_RANK0_NIBBLE2 091
RDLVL_PQTR_RIGHT_RANK0_NIBBLE3 08b
RDLVL_PQTR_RIGHT_RANK0_NIBBLE4 09e
RDLVL_PQTR_RIGHT_RANK0_NIBBLE5 095
RDLVL_PQTR_RIGHT_RANK0_NIBBLE6 097
RDLVL_PQTR_RIGHT_RANK0_NIBBLE7 08d
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE0 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE1 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE2 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE3 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE0 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE1 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE2 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE3 000
READ_VREF_CAL_EYE_SIZE_BYTE0 000
READ_VREF_CAL_EYE_SIZE_BYTE1 000
READ_VREF_CAL_EYE_SIZE_BYTE2 000
READ_VREF_CAL_EYE_SIZE_BYTE3 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE0 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE1 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE2 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE3 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE0 01f
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE1 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE2 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE3 000
RESERVED_LOC6 000
RESERVED_LOC7 000
RESERVED_LOC8 000
RESERVED_LOC9 000
RESERVED_LOC10 000
RESTORE_MODE 000
RL_DLY_QTR_NIBBLE0 03d
RL_DLY_QTR_NIBBLE1 03e
RL_DLY_QTR_NIBBLE2 03e
RL_DLY_QTR_NIBBLE3 03e
RL_DLY_QTR_NIBBLE4 03d
RL_DLY_QTR_NIBBLE5 03e
RL_DLY_QTR_NIBBLE6 03c
RL_DLY_QTR_NIBBLE7 03e
SLOTS 000
SOFT_MIG_CSV_VER 003
START_ADDR 012
TG_MARGIN_CONTROL_0 000
TG_MARGIN_CONTROL_1 000
TG_MARGIN_CONTROL_2 000
TG_MARGIN_CONTROL_3 000
TG_MARGIN_CONTROL_4 000
TG_MARGIN_CONTROL_5 000
TG_MARGIN_CONTROL_6 000
TG_MARGIN_CONTROL_7 000
TG_MARGIN_CONTROL_8 000
TG_MARGIN_CONTROL_9 000
TG_MARGIN_CONTROL_10 000
TG_MARGIN_CONTROL_11 000
TG_MARGIN_CONTROL_12 000
TG_MARGIN_CONTROL_13 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT7 000
USER_REGISTER 1
VT_TRACK_NQTR_MAX_NIBBLE0 04a
VT_TRACK_NQTR_MAX_NIBBLE1 043
VT_TRACK_NQTR_MAX_NIBBLE2 042
VT_TRACK_NQTR_MAX_NIBBLE3 045
VT_TRACK_NQTR_MAX_NIBBLE4 04b
VT_TRACK_NQTR_MAX_NIBBLE5 04b
VT_TRACK_NQTR_MAX_NIBBLE6 046
VT_TRACK_NQTR_MAX_NIBBLE7 046
VT_TRACK_NQTR_MIN_NIBBLE0 04a
VT_TRACK_NQTR_MIN_NIBBLE1 042
VT_TRACK_NQTR_MIN_NIBBLE2 042
VT_TRACK_NQTR_MIN_NIBBLE3 045
VT_TRACK_NQTR_MIN_NIBBLE4 04b
VT_TRACK_NQTR_MIN_NIBBLE5 04b
VT_TRACK_NQTR_MIN_NIBBLE6 045
VT_TRACK_NQTR_MIN_NIBBLE7 046
VT_TRACK_NQTR_NIBBLE0 04a
VT_TRACK_NQTR_NIBBLE1 043
VT_TRACK_NQTR_NIBBLE2 042
VT_TRACK_NQTR_NIBBLE3 045
VT_TRACK_NQTR_NIBBLE4 04b
VT_TRACK_NQTR_NIBBLE5 04b
VT_TRACK_NQTR_NIBBLE6 046
VT_TRACK_NQTR_NIBBLE7 046
VT_TRACK_PQTR_MAX_NIBBLE0 05a
VT_TRACK_PQTR_MAX_NIBBLE1 048
VT_TRACK_PQTR_MAX_NIBBLE2 050
VT_TRACK_PQTR_MAX_NIBBLE3 04a
VT_TRACK_PQTR_MAX_NIBBLE4 05a
VT_TRACK_PQTR_MAX_NIBBLE5 050
VT_TRACK_PQTR_MAX_NIBBLE6 053
VT_TRACK_PQTR_MAX_NIBBLE7 04a
VT_TRACK_PQTR_MIN_NIBBLE0 05a
VT_TRACK_PQTR_MIN_NIBBLE1 047
VT_TRACK_PQTR_MIN_NIBBLE2 050
VT_TRACK_PQTR_MIN_NIBBLE3 04a
VT_TRACK_PQTR_MIN_NIBBLE4 05a
VT_TRACK_PQTR_MIN_NIBBLE5 050
VT_TRACK_PQTR_MIN_NIBBLE6 052
VT_TRACK_PQTR_MIN_NIBBLE7 04a
VT_TRACK_PQTR_NIBBLE0 05a
VT_TRACK_PQTR_NIBBLE1 048
VT_TRACK_PQTR_NIBBLE2 050
VT_TRACK_PQTR_NIBBLE3 04a
VT_TRACK_PQTR_NIBBLE4 05a
VT_TRACK_PQTR_NIBBLE5 050
VT_TRACK_PQTR_NIBBLE6 053
VT_TRACK_PQTR_NIBBLE7 04a
WARNING_COUNT 000
WARNING_MAP_VERSION 001
WARNING_REGISTER_SIZE 003
WNOTICE_COUNT 0
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE0 02b
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE1 039
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE2 00f
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE3 00a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT0 02c
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT1 02d
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT2 02d
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT3 034
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT4 030
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT5 03b
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT6 032
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT7 033
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT0 03a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT1 047
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT2 040
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT3 048
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT4 03b
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT5 045
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT6 046
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT7 040
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT0 014
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT1 014
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT2 015
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT3 015
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT4 01a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT5 019
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT6 016
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT7 015
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT0 00e
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT1 013
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT2 015
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT3 013
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT4 00d
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT5 011
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT6 00e
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT7 011
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE0 02e
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE1 02d
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE2 030
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE3 02f
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE0 02d
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE1 02d
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE2 02f
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE3 02f
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE0 035
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE1 033
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE2 035
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE3 035
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE0 026
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE1 027
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE2 029
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE3 02a
WRITE_DM_ODELAY_FINAL_BYTE0 02b
WRITE_DM_ODELAY_FINAL_BYTE1 03a
WRITE_DM_ODELAY_FINAL_BYTE2 010
WRITE_DM_ODELAY_FINAL_BYTE3 00b
WRITE_DQS_ODELAY_FINAL_BYTE0 02b
WRITE_DQS_ODELAY_FINAL_BYTE1 039
WRITE_DQS_ODELAY_FINAL_BYTE2 00f
WRITE_DQS_ODELAY_FINAL_BYTE3 00a
WRITE_DQS_TO_DM_DESKEW_BYTE0 033
WRITE_DQS_TO_DM_DESKEW_BYTE1 03e
WRITE_DQS_TO_DM_DESKEW_BYTE2 010
WRITE_DQS_TO_DM_DESKEW_BYTE3 00e
WRITE_DQS_TO_DM_DM_ODELAY_BYTE0 02b
WRITE_DQS_TO_DM_DM_ODELAY_BYTE1 03a
WRITE_DQS_TO_DM_DM_ODELAY_BYTE2 010
WRITE_DQS_TO_DM_DM_ODELAY_BYTE3 00b
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE0 032
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE1 03d
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE2 010
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE3 00d
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE0 038
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE1 038
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE2 03b
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE3 03a
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE0 038
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE1 038
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE2 03b
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE3 03a
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE0 034
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE1 038
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE2 039
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE3 037
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE0 03d
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE1 038
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE2 03e
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE3 03d
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE0 02e
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE1 03d
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE2 010
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE3 00c
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE0 02f
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE1 03f
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE2 011
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE3 00c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT0 02c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT1 02d
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT2 02d
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT3 034
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT4 030
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT5 03b
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT6 032
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT7 033
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT0 03a
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT1 047
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT2 040
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT3 048
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT4 03b
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT5 045
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT6 046
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT7 040
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT0 010
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT1 010
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT2 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT3 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT4 016
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT5 015
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT6 012
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT7 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT0 00c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT1 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT2 013
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT3 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT4 00b
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT5 00f
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT6 00c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT7 00f
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE0 039
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE1 038
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE2 039
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE3 039
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE0 03b
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE1 039
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE2 039
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE3 039
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE0 039
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE1 036
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE2 038
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE3 039
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE0 03c
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE1 03b
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE2 03a
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE3 039
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT0 02c
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT1 02d
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT2 02d
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT3 034
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT4 030
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT5 03b
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT6 032
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT7 033
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT0 03a
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT1 047
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT2 040
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT3 048
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT4 03b
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT5 045
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT6 046
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT7 040
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT0 014
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT1 014
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT2 015
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT3 015
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT4 01a
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT5 019
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT6 016
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT7 015
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT0 00e
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT1 013
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT2 015
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT3 013
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT4 00d
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT5 011
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT6 00e
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT7 011
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE0 004
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE1 004
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE2 004
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE3 004
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE3 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE3 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE3 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE0 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE1 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE2 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE3 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE0 014
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE1 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE2 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE3 000
WRLVL_COARSE_STABLE0_RANK0_BYTE0 000
WRLVL_COARSE_STABLE0_RANK0_BYTE1 000
WRLVL_COARSE_STABLE0_RANK0_BYTE2 000
WRLVL_COARSE_STABLE0_RANK0_BYTE3 000
WRLVL_COARSE_STABLE1_RANK0_BYTE0 001
WRLVL_COARSE_STABLE1_RANK0_BYTE1 001
WRLVL_COARSE_STABLE1_RANK0_BYTE2 001
WRLVL_COARSE_STABLE1_RANK0_BYTE3 001
WRLVL_ODELAY_CENTER_RANK0_BYTE0 02a
WRLVL_ODELAY_CENTER_RANK0_BYTE1 039
WRLVL_ODELAY_CENTER_RANK0_BYTE2 00f
WRLVL_ODELAY_CENTER_RANK0_BYTE3 00a
WRLVL_ODELAY_INITIAL_OFFSET_BYTE0 01e
WRLVL_ODELAY_INITIAL_OFFSET_BYTE1 01e
WRLVL_ODELAY_INITIAL_OFFSET_BYTE2 01e
WRLVL_ODELAY_INITIAL_OFFSET_BYTE3 01e
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE0 01e
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE1 01e
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE2 01e
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE3 01e
WRLVL_ODELAY_LOWEST_COMMON_BYTE0 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE1 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE2 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE3 000
WRLVL_ODELAY_STABLE0_RANK0_BYTE0 029
WRLVL_ODELAY_STABLE0_RANK0_BYTE1 037
WRLVL_ODELAY_STABLE0_RANK0_BYTE2 00e
WRLVL_ODELAY_STABLE0_RANK0_BYTE3 008
WRLVL_ODELAY_STABLE1_RANK0_BYTE0 02b
WRLVL_ODELAY_STABLE1_RANK0_BYTE1 03b
WRLVL_ODELAY_STABLE1_RANK0_BYTE2 011
WRLVL_ODELAY_STABLE1_RANK0_BYTE3 00d
XSDB_BRAMS 001
Which contains DQS_GATE_TRACKING FAIL : Underflow of the coarse taps used for tracking. Error found on Rank 0, Byte 1.. UltraScale/UltraScale+ MIG DDR3/DDR4 hardware failure use cases says that error can result in data errors during read/write.
The MIG Status pane in the v2025.2 Hardware Manager has just titles and no status text. If run the v2020.1 Hardware Manager then the MIG Status pane is populated and shows the DQS gate status as FAIL:
On looking again at the v2025.2 Hardware Manager the Status isn't displayed correctly when docked:
But if undock and expand the window then the status is displayed:
I.e. some UI problem.
Looking at the schematic noticed VDD12 is connected to FMC pin C39 which is labeled as 3P3V_3. https://fmchub.github.io/appendix/VITA57_FMC_HPC_LPC_SIGNALS_AND_PINOUT.html indicates C39 is supposed to be 3P3V.
Think that if connect a FMC module which connects the 12V rails together, that would have the effect of shorting the 3.3V and 12V rails together.
Created the XCKU5P_SINGLE_QSFP_dma_ddr4 project. The constraints for the DDR4 were copied from the example file XCKU5P-FFVB676/Demo/KU5P_DDR4_TEST/IO_KU5P.xdc, and verified the pin numbers against the XCKU5P-FFVB676.pdf schematic.
Initially attempted to for maximum performance:
- Memory Frequency: 1333 MHz (data rate 2666 MT/s) which is limited by the FPGA.
DM NO DBIto allow minimum CAS latency 19 and CAS Write Latency 14
After programming the bitstream the Vivado Hardware Manager reports:
- CAL PASS
- DQS_GATE_TRACKING FAIL : Underflow of the coarse taps used for tracking. Error found on Rank 0, Byte 1.
Identity:
$ identify_pcie_fpga_design/display_identified_pcie_fpga_d esigns
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Design XCKU5P_SINGLE_QSFP_dma_ddr4:
PCI device 0000:01:00.0 rev 00 IOMMU group 12
DMA bridge bar 2 memory base offset 0x0 size 0x80000000
Channel ID addr_alignment len_granularity num_address_bits
H2C 0 1 1 64
C2H 0 1 1 64
User access build timestamp : 7B34A0DB - 15/06/2026 10:03:27
UltraScale DNA: 40020000016BE4600CC1C505
Quad SPI registers at bar 0 offset 0x0
SYSMON registers at bar 0 offset 0x1000
Full MIG properties:
2D_EYE_SCAN_END 000
2D_EYE_SCAN_START 000
BISC_ALIGN_NQTR_NIBBLE0 000
BISC_ALIGN_NQTR_NIBBLE1 000
BISC_ALIGN_NQTR_NIBBLE2 000
BISC_ALIGN_NQTR_NIBBLE3 000
BISC_ALIGN_NQTR_NIBBLE4 000
BISC_ALIGN_NQTR_NIBBLE5 000
BISC_ALIGN_NQTR_NIBBLE6 000
BISC_ALIGN_NQTR_NIBBLE7 000
BISC_ALIGN_PQTR_NIBBLE0 00c
BISC_ALIGN_PQTR_NIBBLE1 002
BISC_ALIGN_PQTR_NIBBLE2 00b
BISC_ALIGN_PQTR_NIBBLE3 001
BISC_ALIGN_PQTR_NIBBLE4 00c
BISC_ALIGN_PQTR_NIBBLE5 000
BISC_ALIGN_PQTR_NIBBLE6 00b
BISC_ALIGN_PQTR_NIBBLE7 003
BISC_NQTR_NIBBLE0 036
BISC_NQTR_NIBBLE1 038
BISC_NQTR_NIBBLE2 038
BISC_NQTR_NIBBLE3 039
BISC_NQTR_NIBBLE4 038
BISC_NQTR_NIBBLE5 037
BISC_NQTR_NIBBLE6 037
BISC_NQTR_NIBBLE7 038
BISC_PQTR_NIBBLE0 042
BISC_PQTR_NIBBLE1 038
BISC_PQTR_NIBBLE2 03f
BISC_PQTR_NIBBLE3 039
BISC_PQTR_NIBBLE4 043
BISC_PQTR_NIBBLE5 039
BISC_PQTR_NIBBLE6 040
BISC_PQTR_NIBBLE7 039
BITS_PER_BYTES 008
BIT_TIME 375
BUS_DATA_BURST_0_BIT_0 000
BUS_DATA_BURST_0_BIT_1 000
BUS_DATA_BURST_0_BIT_2 000
BUS_DATA_BURST_0_BIT_3 000
BUS_DATA_BURST_0_BIT_4 000
BUS_DATA_BURST_0_BIT_5 000
BUS_DATA_BURST_0_BIT_6 000
BUS_DATA_BURST_0_BIT_7 000
BUS_DATA_BURST_1_BIT_0 000
BUS_DATA_BURST_1_BIT_1 000
BUS_DATA_BURST_1_BIT_2 000
BUS_DATA_BURST_1_BIT_3 000
BUS_DATA_BURST_1_BIT_4 000
BUS_DATA_BURST_1_BIT_5 000
BUS_DATA_BURST_1_BIT_6 000
BUS_DATA_BURST_1_BIT_7 000
BUS_DATA_BURST_2_BIT_0 000
BUS_DATA_BURST_2_BIT_1 000
BUS_DATA_BURST_2_BIT_2 000
BUS_DATA_BURST_2_BIT_3 000
BUS_DATA_BURST_2_BIT_4 000
BUS_DATA_BURST_2_BIT_5 000
BUS_DATA_BURST_2_BIT_6 000
BUS_DATA_BURST_2_BIT_7 000
BUS_DATA_BURST_3_BIT_0 000
BUS_DATA_BURST_3_BIT_1 000
BUS_DATA_BURST_3_BIT_2 000
BUS_DATA_BURST_3_BIT_3 000
BUS_DATA_BURST_3_BIT_4 000
BUS_DATA_BURST_3_BIT_5 000
BUS_DATA_BURST_3_BIT_6 000
BUS_DATA_BURST_3_BIT_7 000
BYTES 004
CAL_ERROR_MSG No errors detected during calibration.
CAL_MAP_VERSION 001
CAL_STATUS_SIZE 007
CAL_STOP_MARGIN FALSE
CAL_VERSION_C_MB 00b
CAL_VERSION_RTL 007
CELL_NAME XCKU5P_SINGLE_QSFP_dma_ddr4_i/ddr4_0
CLASS hw_mig
CONFIG_INFORMATION_0 0d1
CONFIG_INFORMATION_1 049
CONFIG_INFORMATION_2 004
CONFIG_INFORMATION_3 010
CONFIG_INFORMATION_4 032
CONFIG_INFORMATION_5 049
CONFIG_INFORMATION_6 048
CONFIG_INFORMATION_7 049
CONFIG_INFORMATION_8 0a0
CONFIG_INFORMATION_9 001
CONFIG_INFORMATION_10 014
CONFIG_INFORMATION_11 004
CONFIG_INFORMATION_12 004
CONFIG_INFORMATION_13 004
CONFIG_INFORMATION_14 025
CONFIG_INFORMATION_15 001
CONFIG_INFORMATION_16 000
CONFIG_INFORMATION_17 000
CONFIG_INFORMATION_18 000
CONFIG_INFORMATION_19 021
CONFIG_INFORMATION_20 000
CONFIG_INFORMATION_21 000
CONFIG_INFORMATION_22 000
CONFIG_INFORMATION_23 001
CONFIG_INFORMATION_24 000
CONFIG_INFORMATION_25 001
CONFIG_INFORMATION_26 000
CONFIG_INFORMATION_27 000
CONFIG_INFORMATION_28 000
CONFIG_INFORMATION_29 030
CONFIG_INFORMATION_30 040
CONFIG_INFORMATION_31 050
CONFIG_INFORMATION_32 147
CONTROLLER_INFO 000
CORE_UUID 383D3CF59AA850AA82EC6B834B71E725
DBG_END 001
DDR_CAL_ERROR_0 000
DDR_CAL_ERROR_1 001
DDR_CAL_ERROR_CODE 001
DDR_CAL_STATUS_RANK0_0 0ff
DDR_CAL_STATUS_RANK0_1 1fe
DDR_CAL_STATUS_RANK0_2 1cf
DDR_CAL_STATUS_RANK0_3 01f
DDR_CAL_STATUS_RANK0_4 03f
DDR_CAL_STATUS_RANK0_5 000
DDR_CAL_STATUS_RANK0_6 000
DDR_CAL_STATUS_RANK1_0 000
DDR_CAL_STATUS_RANK1_1 000
DDR_CAL_STATUS_RANK1_2 000
DDR_CAL_STATUS_RANK1_3 000
DDR_CAL_STATUS_RANK1_4 000
DDR_CAL_STATUS_RANK1_5 000
DDR_CAL_STATUS_RANK1_6 000
DDR_CAL_STATUS_RANK2_0 000
DDR_CAL_STATUS_RANK2_1 000
DDR_CAL_STATUS_RANK2_2 000
DDR_CAL_STATUS_RANK2_3 000
DDR_CAL_STATUS_RANK2_4 000
DDR_CAL_STATUS_RANK2_5 000
DDR_CAL_STATUS_RANK2_6 000
DDR_CAL_STATUS_RANK3_0 000
DDR_CAL_STATUS_RANK3_1 000
DDR_CAL_STATUS_RANK3_2 000
DDR_CAL_STATUS_RANK3_3 000
DDR_CAL_STATUS_RANK3_4 000
DDR_CAL_STATUS_RANK3_5 000
DDR_CAL_STATUS_RANK3_6 000
DDR_POST_CAL_STATUS_0 004
DDR_POST_CAL_STATUS_1 000
DDR_POST_CAL_STATUS_2 000
DDR_PRE_CAL_STATUS 01f
DISPLAY_NAME MIG_1
DQS_GATE_COARSE_RANK0_BYTE0 006
DQS_GATE_COARSE_RANK0_BYTE1 006
DQS_GATE_COARSE_RANK0_BYTE2 005
DQS_GATE_COARSE_RANK0_BYTE3 005
DQS_GATE_FINE_CENTER_RANK0_BYTE0 007
DQS_GATE_FINE_CENTER_RANK0_BYTE1 009
DQS_GATE_FINE_CENTER_RANK0_BYTE2 004
DQS_GATE_FINE_CENTER_RANK0_BYTE3 006
DQS_GATE_FINE_LEFT_RANK0_BYTE0 005
DQS_GATE_FINE_LEFT_RANK0_BYTE1 006
DQS_GATE_FINE_LEFT_RANK0_BYTE2 002
DQS_GATE_FINE_LEFT_RANK0_BYTE3 005
DQS_GATE_FINE_RIGHT_RANK0_BYTE0 00a
DQS_GATE_FINE_RIGHT_RANK0_BYTE1 00c
DQS_GATE_FINE_RIGHT_RANK0_BYTE2 006
DQS_GATE_FINE_RIGHT_RANK0_BYTE3 008
DQS_GATE_PATTERN_0_RANK0_BYTE0 198
DQS_GATE_PATTERN_0_RANK0_BYTE1 198
DQS_GATE_PATTERN_0_RANK0_BYTE2 0c0
DQS_GATE_PATTERN_0_RANK0_BYTE3 0c0
DQS_GATE_PATTERN_1_RANK0_BYTE0 000
DQS_GATE_PATTERN_1_RANK0_BYTE1 000
DQS_GATE_PATTERN_1_RANK0_BYTE2 006
DQS_GATE_PATTERN_1_RANK0_BYTE3 006
DQS_GATE_PATTERN_2_RANK0_BYTE0 000
DQS_GATE_PATTERN_2_RANK0_BYTE1 000
DQS_GATE_PATTERN_2_RANK0_BYTE2 000
DQS_GATE_PATTERN_2_RANK0_BYTE3 000
DQS_GATE_READ_LATENCY_RANK0_BYTE0 013
DQS_GATE_READ_LATENCY_RANK0_BYTE1 013
DQS_GATE_READ_LATENCY_RANK0_BYTE2 013
DQS_GATE_READ_LATENCY_RANK0_BYTE3 013
DQS_GATE_TRACKING FAIL : Underflow of the coarse taps used for tracking. Error found on Rank 0, Byte 1.
DQS_TRACK_COARSE_MAX_RANK0_BYTE0 006
DQS_TRACK_COARSE_MAX_RANK0_BYTE1 006
DQS_TRACK_COARSE_MAX_RANK0_BYTE2 005
DQS_TRACK_COARSE_MAX_RANK0_BYTE3 005
DQS_TRACK_COARSE_MIN_RANK0_BYTE0 002
DQS_TRACK_COARSE_MIN_RANK0_BYTE1 000
DQS_TRACK_COARSE_MIN_RANK0_BYTE2 005
DQS_TRACK_COARSE_MIN_RANK0_BYTE3 005
DQS_TRACK_COARSE_RANK0_BYTE0 002
DQS_TRACK_COARSE_RANK0_BYTE1 000
DQS_TRACK_COARSE_RANK0_BYTE2 005
DQS_TRACK_COARSE_RANK0_BYTE3 005
DQS_TRACK_FINE_MAX_RANK0_BYTE0 03a
DQS_TRACK_FINE_MAX_RANK0_BYTE1 037
DQS_TRACK_FINE_MAX_RANK0_BYTE2 006
DQS_TRACK_FINE_MAX_RANK0_BYTE3 009
DQS_TRACK_FINE_MIN_RANK0_BYTE0 000
DQS_TRACK_FINE_MIN_RANK0_BYTE1 000
DQS_TRACK_FINE_MIN_RANK0_BYTE2 003
DQS_TRACK_FINE_MIN_RANK0_BYTE3 006
DQS_TRACK_FINE_RANK0_BYTE0 039
DQS_TRACK_FINE_RANK0_BYTE1 000
DQS_TRACK_FINE_RANK0_BYTE2 005
DQS_TRACK_FINE_RANK0_BYTE3 006
END_ADDR0 041
END_ADDR1 002
ERROR_MAP_VERSION 001
HWM_TOOL_VER 2025.2
MEMORY_CODE_NAME 000
MEMORY_FREQUENCY_0 0ee
MEMORY_FREQUENCY_1 001
MEMORY_MODULE_TYPE 001
MEMORY_VOLTAGE 001
MEM_TYPE 002
MICROBLAZE_START_UP PASS
MIG_REFRESH_RATE 3000
MMCM_D 001
MMCM_M 00a
MR0_0 170
MR0_1 005
MR1_0 101
MR1_1 001
MR2_0 020
MR2_1 000
MR3_0 000
MR3_1 002
MR4_0 000
MR4_1 000
MR5_0 000
MR5_1 002
MR6_0 014
MR6_1 006
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE0 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE1 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE2 000
MULTI_RANK_DQS_GATE_COARSE_RANK0_BYTE3 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE0 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE1 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE2 000
MULTI_RANK_DQS_GATE_READ_LATENCY_BYTE3 000
NAME localhost:3121/xilinx_tcf/Digilent/210512180081/0_1/MIG_1
NIBBLES 008
NUM_RANK 001
PERIOD 750
PLL_D 001
PLL_M 004
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE0 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE1 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE2 000
RDLVL_COMPLEX_IDELAY_DBI_RANK0_BYTE3 000
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT0 039
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT1 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT2 049
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT3 04e
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT4 03c
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT5 03f
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT6 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE0_BIT7 039
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT0 040
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT1 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT2 049
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT3 044
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT4 044
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT5 039
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT6 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE1_BIT7 042
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT0 04a
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT1 04b
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT2 050
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT3 043
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT4 04c
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT5 041
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT6 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE2_BIT7 041
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT0 045
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT1 042
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT2 04b
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT3 049
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT4 046
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT5 041
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT6 041
RDLVL_COMPLEX_IDELAY_RANK0_BYTE3_BIT7 043
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE0 046
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE1 040
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE2 03e
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE3 03f
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE4 044
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE5 042
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE6 03f
RDLVL_COMPLEX_NQTR_CENTER_RANK0_NIBBLE7 041
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE0 023
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE1 01c
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE2 019
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE3 01a
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE4 01f
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE5 01e
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE6 019
RDLVL_COMPLEX_NQTR_LEFT_RANK0_NIBBLE7 01d
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE0 06a
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE1 064
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE2 064
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE3 064
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE4 06a
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE5 067
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE6 065
RDLVL_COMPLEX_NQTR_RIGHT_RANK0_NIBBLE7 065
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE0 056
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE1 044
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE2 04a
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE3 043
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE4 056
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE5 049
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE6 04e
RDLVL_COMPLEX_PQTR_CENTER_RANK0_NIBBLE7 046
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE0 033
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE1 021
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE2 024
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE3 01d
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE4 032
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE5 025
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE6 027
RDLVL_COMPLEX_PQTR_LEFT_RANK0_NIBBLE7 020
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE0 079
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE1 068
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE2 071
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE3 069
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE4 07a
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE5 06e
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE6 075
RDLVL_COMPLEX_PQTR_RIGHT_RANK0_NIBBLE7 06d
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE0 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE1 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE2 000
RDLVL_DBI_NQTR_CENTER_RANK0_BYTE3 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE0 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE1 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE2 000
RDLVL_DBI_NQTR_LEFT_RANK0_BYTE3 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE0 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE1 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE2 000
RDLVL_DBI_NQTR_RIGHT_RANK0_BYTE3 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE0 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE1 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE2 000
RDLVL_DBI_PQTR_CENTER_RANK0_BYTE3 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE0 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE1 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE2 000
RDLVL_DBI_PQTR_LEFT_RANK0_BYTE3 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE0 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE1 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE2 000
RDLVL_DBI_PQTR_RIGHT_RANK0_BYTE3 000
RDLVL_DESKEW_DBI_IDELAY_BYTE0 000
RDLVL_DESKEW_DBI_IDELAY_BYTE1 000
RDLVL_DESKEW_DBI_IDELAY_BYTE2 000
RDLVL_DESKEW_DBI_IDELAY_BYTE3 000
RDLVL_DESKEW_DBI_NQTR_BYTE0 000
RDLVL_DESKEW_DBI_NQTR_BYTE1 000
RDLVL_DESKEW_DBI_NQTR_BYTE2 000
RDLVL_DESKEW_DBI_NQTR_BYTE3 000
RDLVL_DESKEW_DBI_PQTR_BYTE0 000
RDLVL_DESKEW_DBI_PQTR_BYTE1 000
RDLVL_DESKEW_DBI_PQTR_BYTE2 000
RDLVL_DESKEW_DBI_PQTR_BYTE3 000
RDLVL_DESKEW_IDELAY_BYTE0_BIT0 01d
RDLVL_DESKEW_IDELAY_BYTE0_BIT1 02a
RDLVL_DESKEW_IDELAY_BYTE0_BIT2 02b
RDLVL_DESKEW_IDELAY_BYTE0_BIT3 02c
RDLVL_DESKEW_IDELAY_BYTE0_BIT4 023
RDLVL_DESKEW_IDELAY_BYTE0_BIT5 027
RDLVL_DESKEW_IDELAY_BYTE0_BIT6 028
RDLVL_DESKEW_IDELAY_BYTE0_BIT7 01e
RDLVL_DESKEW_IDELAY_BYTE1_BIT0 02a
RDLVL_DESKEW_IDELAY_BYTE1_BIT1 02d
RDLVL_DESKEW_IDELAY_BYTE1_BIT2 032
RDLVL_DESKEW_IDELAY_BYTE1_BIT3 031
RDLVL_DESKEW_IDELAY_BYTE1_BIT4 02f
RDLVL_DESKEW_IDELAY_BYTE1_BIT5 021
RDLVL_DESKEW_IDELAY_BYTE1_BIT6 02d
RDLVL_DESKEW_IDELAY_BYTE1_BIT7 02a
RDLVL_DESKEW_IDELAY_BYTE2_BIT0 028
RDLVL_DESKEW_IDELAY_BYTE2_BIT1 02d
RDLVL_DESKEW_IDELAY_BYTE2_BIT2 032
RDLVL_DESKEW_IDELAY_BYTE2_BIT3 028
RDLVL_DESKEW_IDELAY_BYTE2_BIT4 02d
RDLVL_DESKEW_IDELAY_BYTE2_BIT5 022
RDLVL_DESKEW_IDELAY_BYTE2_BIT6 027
RDLVL_DESKEW_IDELAY_BYTE2_BIT7 024
RDLVL_DESKEW_IDELAY_BYTE3_BIT0 02a
RDLVL_DESKEW_IDELAY_BYTE3_BIT1 026
RDLVL_DESKEW_IDELAY_BYTE3_BIT2 02e
RDLVL_DESKEW_IDELAY_BYTE3_BIT3 02e
RDLVL_DESKEW_IDELAY_BYTE3_BIT4 02b
RDLVL_DESKEW_IDELAY_BYTE3_BIT5 027
RDLVL_DESKEW_IDELAY_BYTE3_BIT6 029
RDLVL_DESKEW_IDELAY_BYTE3_BIT7 028
RDLVL_DESKEW_NQTR_NIBBLE0 000
RDLVL_DESKEW_NQTR_NIBBLE1 000
RDLVL_DESKEW_NQTR_NIBBLE2 000
RDLVL_DESKEW_NQTR_NIBBLE3 000
RDLVL_DESKEW_NQTR_NIBBLE4 000
RDLVL_DESKEW_NQTR_NIBBLE5 000
RDLVL_DESKEW_NQTR_NIBBLE6 000
RDLVL_DESKEW_NQTR_NIBBLE7 000
RDLVL_DESKEW_PQTR_NIBBLE0 00c
RDLVL_DESKEW_PQTR_NIBBLE1 000
RDLVL_DESKEW_PQTR_NIBBLE2 007
RDLVL_DESKEW_PQTR_NIBBLE3 000
RDLVL_DESKEW_PQTR_NIBBLE4 00b
RDLVL_DESKEW_PQTR_NIBBLE5 002
RDLVL_DESKEW_PQTR_NIBBLE6 009
RDLVL_DESKEW_PQTR_NIBBLE7 001
RDLVL_IDELAY_DBI_FINAL_BYTE0 000
RDLVL_IDELAY_DBI_FINAL_BYTE1 000
RDLVL_IDELAY_DBI_FINAL_BYTE2 000
RDLVL_IDELAY_DBI_FINAL_BYTE3 000
RDLVL_IDELAY_DBI_RANK0_BYTE0 000
RDLVL_IDELAY_DBI_RANK0_BYTE1 000
RDLVL_IDELAY_DBI_RANK0_BYTE2 000
RDLVL_IDELAY_DBI_RANK0_BYTE3 000
RDLVL_IDELAY_FINAL_BYTE0_BIT0 039
RDLVL_IDELAY_FINAL_BYTE0_BIT1 045
RDLVL_IDELAY_FINAL_BYTE0_BIT2 049
RDLVL_IDELAY_FINAL_BYTE0_BIT3 04e
RDLVL_IDELAY_FINAL_BYTE0_BIT4 03c
RDLVL_IDELAY_FINAL_BYTE0_BIT5 03f
RDLVL_IDELAY_FINAL_BYTE0_BIT6 046
RDLVL_IDELAY_FINAL_BYTE0_BIT7 039
RDLVL_IDELAY_FINAL_BYTE1_BIT0 040
RDLVL_IDELAY_FINAL_BYTE1_BIT1 045
RDLVL_IDELAY_FINAL_BYTE1_BIT2 049
RDLVL_IDELAY_FINAL_BYTE1_BIT3 044
RDLVL_IDELAY_FINAL_BYTE1_BIT4 044
RDLVL_IDELAY_FINAL_BYTE1_BIT5 039
RDLVL_IDELAY_FINAL_BYTE1_BIT6 046
RDLVL_IDELAY_FINAL_BYTE1_BIT7 042
RDLVL_IDELAY_FINAL_BYTE2_BIT0 04a
RDLVL_IDELAY_FINAL_BYTE2_BIT1 04b
RDLVL_IDELAY_FINAL_BYTE2_BIT2 050
RDLVL_IDELAY_FINAL_BYTE2_BIT3 043
RDLVL_IDELAY_FINAL_BYTE2_BIT4 04c
RDLVL_IDELAY_FINAL_BYTE2_BIT5 041
RDLVL_IDELAY_FINAL_BYTE2_BIT6 045
RDLVL_IDELAY_FINAL_BYTE2_BIT7 041
RDLVL_IDELAY_FINAL_BYTE3_BIT0 045
RDLVL_IDELAY_FINAL_BYTE3_BIT1 042
RDLVL_IDELAY_FINAL_BYTE3_BIT2 04b
RDLVL_IDELAY_FINAL_BYTE3_BIT3 049
RDLVL_IDELAY_FINAL_BYTE3_BIT4 046
RDLVL_IDELAY_FINAL_BYTE3_BIT5 041
RDLVL_IDELAY_FINAL_BYTE3_BIT6 041
RDLVL_IDELAY_FINAL_BYTE3_BIT7 043
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT0 039
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT1 045
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT2 049
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT3 04e
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT4 03c
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT5 03f
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT6 046
RDLVL_IDELAY_VALUE_RANK0_BYTE0_BIT7 039
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT0 040
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT1 045
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT2 049
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT3 044
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT4 044
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT5 039
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT6 046
RDLVL_IDELAY_VALUE_RANK0_BYTE1_BIT7 042
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT0 04a
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT1 04b
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT2 050
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT3 043
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT4 04c
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT5 041
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT6 045
RDLVL_IDELAY_VALUE_RANK0_BYTE2_BIT7 041
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT0 045
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT1 042
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT2 04b
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT3 049
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT4 046
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT5 041
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT6 041
RDLVL_IDELAY_VALUE_RANK0_BYTE3_BIT7 043
RDLVL_NQTR_CENTER_FINAL_NIBBLE0 046
RDLVL_NQTR_CENTER_FINAL_NIBBLE1 040
RDLVL_NQTR_CENTER_FINAL_NIBBLE2 03e
RDLVL_NQTR_CENTER_FINAL_NIBBLE3 03f
RDLVL_NQTR_CENTER_FINAL_NIBBLE4 044
RDLVL_NQTR_CENTER_FINAL_NIBBLE5 042
RDLVL_NQTR_CENTER_FINAL_NIBBLE6 03f
RDLVL_NQTR_CENTER_FINAL_NIBBLE7 041
RDLVL_NQTR_CENTER_RANK0_NIBBLE0 04b
RDLVL_NQTR_CENTER_RANK0_NIBBLE1 044
RDLVL_NQTR_CENTER_RANK0_NIBBLE2 043
RDLVL_NQTR_CENTER_RANK0_NIBBLE3 043
RDLVL_NQTR_CENTER_RANK0_NIBBLE4 049
RDLVL_NQTR_CENTER_RANK0_NIBBLE5 047
RDLVL_NQTR_CENTER_RANK0_NIBBLE6 043
RDLVL_NQTR_CENTER_RANK0_NIBBLE7 045
RDLVL_NQTR_LEFT_RANK0_NIBBLE0 021
RDLVL_NQTR_LEFT_RANK0_NIBBLE1 01a
RDLVL_NQTR_LEFT_RANK0_NIBBLE2 018
RDLVL_NQTR_LEFT_RANK0_NIBBLE3 017
RDLVL_NQTR_LEFT_RANK0_NIBBLE4 01e
RDLVL_NQTR_LEFT_RANK0_NIBBLE5 01c
RDLVL_NQTR_LEFT_RANK0_NIBBLE6 018
RDLVL_NQTR_LEFT_RANK0_NIBBLE7 01b
RDLVL_NQTR_RIGHT_RANK0_NIBBLE0 076
RDLVL_NQTR_RIGHT_RANK0_NIBBLE1 06f
RDLVL_NQTR_RIGHT_RANK0_NIBBLE2 06e
RDLVL_NQTR_RIGHT_RANK0_NIBBLE3 070
RDLVL_NQTR_RIGHT_RANK0_NIBBLE4 075
RDLVL_NQTR_RIGHT_RANK0_NIBBLE5 073
RDLVL_NQTR_RIGHT_RANK0_NIBBLE6 06f
RDLVL_NQTR_RIGHT_RANK0_NIBBLE7 070
RDLVL_PQTR_CENTER_FINAL_NIBBLE0 056
RDLVL_PQTR_CENTER_FINAL_NIBBLE1 044
RDLVL_PQTR_CENTER_FINAL_NIBBLE2 04a
RDLVL_PQTR_CENTER_FINAL_NIBBLE3 043
RDLVL_PQTR_CENTER_FINAL_NIBBLE4 056
RDLVL_PQTR_CENTER_FINAL_NIBBLE5 049
RDLVL_PQTR_CENTER_FINAL_NIBBLE6 04e
RDLVL_PQTR_CENTER_FINAL_NIBBLE7 046
RDLVL_PQTR_CENTER_RANK0_NIBBLE0 055
RDLVL_PQTR_CENTER_RANK0_NIBBLE1 045
RDLVL_PQTR_CENTER_RANK0_NIBBLE2 04c
RDLVL_PQTR_CENTER_RANK0_NIBBLE3 044
RDLVL_PQTR_CENTER_RANK0_NIBBLE4 055
RDLVL_PQTR_CENTER_RANK0_NIBBLE5 04b
RDLVL_PQTR_CENTER_RANK0_NIBBLE6 04d
RDLVL_PQTR_CENTER_RANK0_NIBBLE7 045
RDLVL_PQTR_LEFT_RANK0_NIBBLE0 01a
RDLVL_PQTR_LEFT_RANK0_NIBBLE1 00b
RDLVL_PQTR_LEFT_RANK0_NIBBLE2 010
RDLVL_PQTR_LEFT_RANK0_NIBBLE3 009
RDLVL_PQTR_LEFT_RANK0_NIBBLE4 01a
RDLVL_PQTR_LEFT_RANK0_NIBBLE5 00f
RDLVL_PQTR_LEFT_RANK0_NIBBLE6 010
RDLVL_PQTR_LEFT_RANK0_NIBBLE7 008
RDLVL_PQTR_RIGHT_RANK0_NIBBLE0 091
RDLVL_PQTR_RIGHT_RANK0_NIBBLE1 080
RDLVL_PQTR_RIGHT_RANK0_NIBBLE2 088
RDLVL_PQTR_RIGHT_RANK0_NIBBLE3 080
RDLVL_PQTR_RIGHT_RANK0_NIBBLE4 091
RDLVL_PQTR_RIGHT_RANK0_NIBBLE5 087
RDLVL_PQTR_RIGHT_RANK0_NIBBLE6 08a
RDLVL_PQTR_RIGHT_RANK0_NIBBLE7 083
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE0 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE1 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE2 000
READ_VREF_CAL_EYE_LEFT_EDGE_BYTE3 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE0 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE1 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE2 000
READ_VREF_CAL_EYE_RIGHT_EDGE_BYTE3 000
READ_VREF_CAL_EYE_SIZE_BYTE0 000
READ_VREF_CAL_EYE_SIZE_BYTE1 000
READ_VREF_CAL_EYE_SIZE_BYTE2 000
READ_VREF_CAL_EYE_SIZE_BYTE3 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE0 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE1 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE2 000
READ_VREF_CAL_VREF_COARSE_VALUE_BYTE3 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE0 01f
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE1 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE2 000
READ_VREF_CAL_VREF_FINAL_VALUE_BYTE3 000
RESERVED_LOC6 000
RESERVED_LOC7 000
RESERVED_LOC8 000
RESERVED_LOC9 000
RESERVED_LOC10 000
RESTORE_MODE 000
RL_DLY_QTR_NIBBLE0 036
RL_DLY_QTR_NIBBLE1 038
RL_DLY_QTR_NIBBLE2 038
RL_DLY_QTR_NIBBLE3 037
RL_DLY_QTR_NIBBLE4 037
RL_DLY_QTR_NIBBLE5 038
RL_DLY_QTR_NIBBLE6 036
RL_DLY_QTR_NIBBLE7 037
SLOTS 000
SOFT_MIG_CSV_VER 003
START_ADDR 012
TG_MARGIN_CONTROL_0 000
TG_MARGIN_CONTROL_1 000
TG_MARGIN_CONTROL_2 000
TG_MARGIN_CONTROL_3 000
TG_MARGIN_CONTROL_4 000
TG_MARGIN_CONTROL_5 000
TG_MARGIN_CONTROL_6 000
TG_MARGIN_CONTROL_7 000
TG_MARGIN_CONTROL_8 000
TG_MARGIN_CONTROL_9 000
TG_MARGIN_CONTROL_10 000
TG_MARGIN_CONTROL_11 000
TG_MARGIN_CONTROL_12 000
TG_MARGIN_CONTROL_13 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_NQTR_LEFT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_NQTR_RIGHT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_PQTR_LEFT_RANK0_BYTE3_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE0_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE1_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE2_BIT7 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT0 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT1 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT2 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT3 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT4 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT5 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT6 000
TG_RDLVL_MARGIN_PQTR_RIGHT_RANK0_BYTE3_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE0_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE1_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE2_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_LEFT_RANK0_BYTE3_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE0_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE1_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE2_BIT7 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT0 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT1 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT2 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT3 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT4 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT5 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT6 000
TG_WRITE_DQS_DQ_MARGIN_RIGHT_RANK0_BYTE3_BIT7 000
USER_REGISTER 1
VT_TRACK_NQTR_MAX_NIBBLE0 046
VT_TRACK_NQTR_MAX_NIBBLE1 03f
VT_TRACK_NQTR_MAX_NIBBLE2 03e
VT_TRACK_NQTR_MAX_NIBBLE3 03f
VT_TRACK_NQTR_MAX_NIBBLE4 044
VT_TRACK_NQTR_MAX_NIBBLE5 042
VT_TRACK_NQTR_MAX_NIBBLE6 03f
VT_TRACK_NQTR_MAX_NIBBLE7 041
VT_TRACK_NQTR_MIN_NIBBLE0 045
VT_TRACK_NQTR_MIN_NIBBLE1 03f
VT_TRACK_NQTR_MIN_NIBBLE2 03d
VT_TRACK_NQTR_MIN_NIBBLE3 03f
VT_TRACK_NQTR_MIN_NIBBLE4 043
VT_TRACK_NQTR_MIN_NIBBLE5 041
VT_TRACK_NQTR_MIN_NIBBLE6 03f
VT_TRACK_NQTR_MIN_NIBBLE7 040
VT_TRACK_NQTR_NIBBLE0 045
VT_TRACK_NQTR_NIBBLE1 03f
VT_TRACK_NQTR_NIBBLE2 03d
VT_TRACK_NQTR_NIBBLE3 03f
VT_TRACK_NQTR_NIBBLE4 044
VT_TRACK_NQTR_NIBBLE5 042
VT_TRACK_NQTR_NIBBLE6 03f
VT_TRACK_NQTR_NIBBLE7 041
VT_TRACK_PQTR_MAX_NIBBLE0 056
VT_TRACK_PQTR_MAX_NIBBLE1 043
VT_TRACK_PQTR_MAX_NIBBLE2 04a
VT_TRACK_PQTR_MAX_NIBBLE3 043
VT_TRACK_PQTR_MAX_NIBBLE4 056
VT_TRACK_PQTR_MAX_NIBBLE5 049
VT_TRACK_PQTR_MAX_NIBBLE6 04e
VT_TRACK_PQTR_MAX_NIBBLE7 046
VT_TRACK_PQTR_MIN_NIBBLE0 055
VT_TRACK_PQTR_MIN_NIBBLE1 043
VT_TRACK_PQTR_MIN_NIBBLE2 049
VT_TRACK_PQTR_MIN_NIBBLE3 043
VT_TRACK_PQTR_MIN_NIBBLE4 055
VT_TRACK_PQTR_MIN_NIBBLE5 048
VT_TRACK_PQTR_MIN_NIBBLE6 04e
VT_TRACK_PQTR_MIN_NIBBLE7 045
VT_TRACK_PQTR_NIBBLE0 055
VT_TRACK_PQTR_NIBBLE1 043
VT_TRACK_PQTR_NIBBLE2 049
VT_TRACK_PQTR_NIBBLE3 043
VT_TRACK_PQTR_NIBBLE4 056
VT_TRACK_PQTR_NIBBLE5 049
VT_TRACK_PQTR_NIBBLE6 04e
VT_TRACK_PQTR_NIBBLE7 046
WARNING_COUNT 000
WARNING_MAP_VERSION 001
WARNING_REGISTER_SIZE 003
WNOTICE_COUNT 0
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_DM_ODELAY_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_DQS_ODELAY_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_LEFT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_MARGIN_RIGHT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE0 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE1 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE2 000
WRITE_COMPLEX_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE3 000
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE0 02e
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE1 004
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE2 015
WRITE_COMPLEX_DQS_TO_DQ_DQS_ODELAY_BYTE3 00f
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT0 030
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT1 031
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT2 030
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT3 038
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT4 034
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT5 03f
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT6 036
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT7 037
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT0 008
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT1 015
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT2 00f
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT3 016
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT4 00a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT5 013
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT6 014
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT7 011
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT0 018
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT1 018
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT2 01a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT3 01a
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT4 01f
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT5 01e
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT6 018
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT7 019
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT0 014
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT1 019
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT2 01b
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT3 018
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT4 012
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT5 019
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT6 014
WRITE_COMPLEX_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT7 017
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE0 028
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE1 028
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE2 02b
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_LEFT_BYTE3 029
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE0 027
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE1 025
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE2 028
WRITE_COMPLEX_DQS_TO_DQ_MARGIN_RIGHT_BYTE3 02a
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE0 02e
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE1 02d
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE2 030
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE3 02e
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE0 020
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE1 022
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE2 023
WRITE_COMPLEX_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE3 024
WRITE_DM_ODELAY_FINAL_BYTE0 02f
WRITE_DM_ODELAY_FINAL_BYTE1 005
WRITE_DM_ODELAY_FINAL_BYTE2 017
WRITE_DM_ODELAY_FINAL_BYTE3 010
WRITE_DQS_ODELAY_FINAL_BYTE0 02e
WRITE_DQS_ODELAY_FINAL_BYTE1 004
WRITE_DQS_ODELAY_FINAL_BYTE2 015
WRITE_DQS_ODELAY_FINAL_BYTE3 00f
WRITE_DQS_TO_DM_DESKEW_BYTE0 036
WRITE_DQS_TO_DM_DESKEW_BYTE1 00b
WRITE_DQS_TO_DM_DESKEW_BYTE2 016
WRITE_DQS_TO_DM_DESKEW_BYTE3 012
WRITE_DQS_TO_DM_DM_ODELAY_BYTE0 02f
WRITE_DQS_TO_DM_DM_ODELAY_BYTE1 005
WRITE_DQS_TO_DM_DM_ODELAY_BYTE2 017
WRITE_DQS_TO_DM_DM_ODELAY_BYTE3 010
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE0 034
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE1 006
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE2 019
WRITE_DQS_TO_DM_DQS_ODELAY_BYTE3 012
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE0 032
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE1 032
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE2 035
WRITE_DQS_TO_DM_MARGIN_LEFT_BYTE3 033
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE0 032
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE1 032
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE2 035
WRITE_DQS_TO_DM_MARGIN_RIGHT_BYTE3 033
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE0 02e
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE1 035
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE2 034
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_LEFT_BYTE3 032
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE0 037
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE1 02f
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE2 036
WRITE_DQS_TO_DM_PRE_ADJUST_MARGIN_RIGHT_BYTE3 035
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE0 031
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE1 00a
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE2 016
WRITE_DQS_TO_DQ_DESKEW_DELAY_BYTE3 011
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE0 032
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE1 007
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE2 019
WRITE_DQS_TO_DQ_DQS_ODELAY_BYTE3 012
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT0 02f
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT1 030
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT2 02f
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT3 037
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT4 033
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT5 03e
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT6 035
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE0_BIT7 036
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT0 005
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT1 012
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT2 00c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT3 013
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT4 007
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT5 010
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT6 011
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE1_BIT7 00e
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT0 016
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT1 016
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT2 018
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT3 018
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT4 01d
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT5 01c
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT6 016
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE2_BIT7 017
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT0 012
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT1 017
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT2 019
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT3 016
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT4 010
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT5 017
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT6 012
WRITE_DQS_TO_DQ_DQ_ODELAY_BYTE3_BIT7 015
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE0 033
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE1 031
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE2 033
WRITE_DQS_TO_DQ_MARGIN_LEFT_BYTE3 033
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE0 033
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE1 031
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE2 034
WRITE_DQS_TO_DQ_MARGIN_RIGHT_BYTE3 033
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE0 032
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE1 035
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE2 030
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_LEFT_BYTE3 031
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE0 034
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE1 02e
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE2 037
WRITE_DQS_TO_DQ_PRE_ADJUST_MARGIN_RIGHT_BYTE3 034
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT0 030
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT1 031
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT2 030
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT3 038
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT4 034
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT5 03f
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT6 036
WRITE_DQ_ODELAY_FINAL_BYTE0_BIT7 037
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT0 008
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT1 015
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT2 00f
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT3 016
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT4 00a
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT5 013
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT6 014
WRITE_DQ_ODELAY_FINAL_BYTE1_BIT7 011
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT0 018
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT1 018
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT2 01a
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT3 01a
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT4 01f
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT5 01e
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT6 018
WRITE_DQ_ODELAY_FINAL_BYTE2_BIT7 019
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT0 014
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT1 019
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT2 01b
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT3 018
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT4 012
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT5 019
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT6 014
WRITE_DQ_ODELAY_FINAL_BYTE3_BIT7 017
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE0 004
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE1 005
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE2 004
WRITE_LATENCY_CALIBRATION_COARSE_RANK0_BYTE3 004
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_LEFT_EDGE_RANK0_BYTE3 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_RIGHT_EDGE_RANK0_BYTE3 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE0 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE1 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE2 000
WRITE_VREF_CAL_EYE_SIZE_RANK0_BYTE3 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE0 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE1 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE2 000
WRITE_VREF_CAL_VREF_COARSE_VALUE_RANK0_BYTE3 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE0 014
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE1 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE2 000
WRITE_VREF_CAL_VREF_FINAL_VALUE_RANK0_BYTE3 000
WRLVL_COARSE_STABLE0_RANK0_BYTE0 000
WRLVL_COARSE_STABLE0_RANK0_BYTE1 001
WRLVL_COARSE_STABLE0_RANK0_BYTE2 000
WRLVL_COARSE_STABLE0_RANK0_BYTE3 000
WRLVL_COARSE_STABLE1_RANK0_BYTE0 001
WRLVL_COARSE_STABLE1_RANK0_BYTE1 002
WRLVL_COARSE_STABLE1_RANK0_BYTE2 001
WRLVL_COARSE_STABLE1_RANK0_BYTE3 001
WRLVL_ODELAY_CENTER_RANK0_BYTE0 02e
WRLVL_ODELAY_CENTER_RANK0_BYTE1 004
WRLVL_ODELAY_CENTER_RANK0_BYTE2 015
WRLVL_ODELAY_CENTER_RANK0_BYTE3 00f
WRLVL_ODELAY_INITIAL_OFFSET_BYTE0 01b
WRLVL_ODELAY_INITIAL_OFFSET_BYTE1 01b
WRLVL_ODELAY_INITIAL_OFFSET_BYTE2 01b
WRLVL_ODELAY_INITIAL_OFFSET_BYTE3 01b
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE0 01b
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE1 01b
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE2 01b
WRLVL_ODELAY_LAST_OFFSET_RANK0_BYTE3 01b
WRLVL_ODELAY_LOWEST_COMMON_BYTE0 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE1 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE2 000
WRLVL_ODELAY_LOWEST_COMMON_BYTE3 000
WRLVL_ODELAY_STABLE0_RANK0_BYTE0 02d
WRLVL_ODELAY_STABLE0_RANK0_BYTE1 003
WRLVL_ODELAY_STABLE0_RANK0_BYTE2 014
WRLVL_ODELAY_STABLE0_RANK0_BYTE3 00e
WRLVL_ODELAY_STABLE1_RANK0_BYTE0 030
WRLVL_ODELAY_STABLE1_RANK0_BYTE1 005
WRLVL_ODELAY_STABLE1_RANK0_BYTE2 017
WRLVL_ODELAY_STABLE1_RANK0_BYTE3 011
XSDB_BRAMS 001
Calibration is read back as completed by the software:
$ xilinx_dma_bridge_for_pcie/ddr3_reset_control
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Current reset signal state:
locked : 1
mmcm_locked : 1
init_cal_complete: 1
ui_clk_sync_rst : 0
But incorrect data is readback:
$ xilinx_dma_bridge_for_pcie/test_dma_descriptor_credits
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Testing DMA bridge bar 2 memory base offset 0x0 size 0x80000000
Testing 12570624 bytes of card memory, using rings with 1023 descriptors, and a total of 3069 descriptors
card_words[0] actual=0x8faaa38f expected=0x00000000
Test: FAIL
$ xilinx_dma_bridge_for_pcie/test_dma_bridge
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Testing XCKU5P_SINGLE_QSFP_dma_ddr4 design with memory base address 0x0 size 0x80000000
PCI device 0000:01:00.0 IOMMU group 12
Testing using 16 buffers of size 0x8000000 bytes, H2C channel 0 C2H channel 0
TEST FAIL:
C2H failure : DDR word[0] actual=0xffffffff expected=0x0
Testing XCKU5P_SINGLE_QSFP_dma_ddr4 design with memory base address 0x0 size 0x80000000
PCI device 0000:01:00.0 IOMMU group 12
Testing using:
H2C channel 0 transfer length 0x10000000 bytes with 16 descriptors
C2H channel 0 transfer length 0x10000000 bytes with 16 descriptors
TEST FAIL:
C2H failure : DDR word[0] actual=0xffffffff expected=0x0
Overall FAIL
Performed a reset (clocking_wizard_locked is hard-wired as a 1 in the FPGA):
$ xilinx_dma_bridge_for_pcie/ddr3_reset_control -r 0.1
Opening device 0000:01:00.0 (10ee:9038) with IOMMU group 12
Enabled bus master for 0000:01:00.0
Applying DDR3 reset...
Time (secs) clocking_wizard_reset clocking_wizard_locked mmcm_locked init_cal_complete ui_clk_sync_rst_mask
0.000000000 0 1 1 1 0
0.000006995 1 1 0 0 1
0.100000848 0 1 0 0 1
0.100022595 0 1 1 0 0
0.389015971 0 1 1 1 0
Which shows after releasing reset:
- Takes ~23 us for MMCM to lock
- Takes ~289 ms for calibration to complete
Following the reset, didn't change the behaviour:
- Still read back incorrect data
- Same DQS gate status fail
Comparing the MIG properties against the example programmed in flash shows the example is using the slower DDR4-2400 data rate, rather than the DDR4-2666 attempted with XCKU5P_SINGLE_QSFP_dma_ddr4.
Changed the CONFIG.C0.DDR4_TimePeriod from 750 (DDR4-2666) to 1250 (DDR4-1600) which should be the slowest DDR4 data rate. That didn't change the symptoms. Confirmed that the Memory Frequency (MHz) reported in the Hardware Manager for the MIG core was 800 following the change.
Differences in create_project.tcl:
diff --git a/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl b/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
index bf60788..651f267 100644
--- a/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
+++ b/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
@@ -3,7 +3,7 @@
#
# create_project.tcl: Tcl script for re-creating project 'XCKU5P_SINGLE_QSFP_dma_ddr4'
#
-# Generated by Vivado on Mon Jun 15 10:11:20 BST 2026
+# Generated by Vivado on Mon Jun 15 22:47:30 BST 2026
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -447,6 +447,7 @@ proc cr_bd_XCKU5P_SINGLE_QSFP_dma_ddr4 { parentCell } {
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {10000} \
CONFIG.C0.DDR4_MemoryPart {MT40A512M16TB-062E} \
+ CONFIG.C0.DDR4_TimePeriod {1250} \
CONFIG.Debug_Signal {Enable} \
CONFIG.System_Clock {Differential} \
] $ddr4_0As didn't fix the problem, didn't commit the changes.
As well as reducing data rate to DDR4-1600 also tried enabled read DBI:
diff --git a/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl b/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
index bf60788..cc685b2 100644
--- a/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
+++ b/fpga_tests/XCKU5P_SINGLE_QSFP_dma_ddr4/create_project.tcl
@@ -3,7 +3,7 @@
#
# create_project.tcl: Tcl script for re-creating project 'XCKU5P_SINGLE_QSFP_dma_ddr4'
#
-# Generated by Vivado on Mon Jun 15 10:11:20 BST 2026
+# Generated by Vivado on Tue Jun 16 20:58:26 BST 2026
# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -443,10 +443,11 @@ proc cr_bd_XCKU5P_SINGLE_QSFP_dma_ddr4 { parentCell } {
# Create instance: ddr4_0, and set properties
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
set_property -dict [list \
- CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
+ CONFIG.C0.DDR4_DataMask {DM_DBI_RD} \
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {10000} \
CONFIG.C0.DDR4_MemoryPart {MT40A512M16TB-062E} \
+ CONFIG.C0.DDR4_TimePeriod {1250} \
CONFIG.Debug_Signal {Enable} \
CONFIG.System_Clock {Differential} \
] $ddr4_0This didn't change the symptoms.
The example constraints had the following:
set_property INTERNAL_VREF 0.6 [get_iobanks 66]
set_property INTERNAL_VREF 0.6 [get_iobanks 65]The VREF for POD12 or POD12_DCI in UG571 is shown as 0.84. Removed the above property, but didn't change the symptoms. Looking at the generated schematic shows FABRIC_VREF_TUNE being used to control the VREF for the DDR4 IOBs, so not sure exactly what the INTERNAL_VREF was controlling.